Nokia 9110 Service Manual
PAMS
Technical Documentation
RAE–2
Baseband
Page 2– 39
Original 02/99
13MHz internal clock for the MCU and system logic blocks and a 13MHz
clock for the DSP, where it is multiplied to 45.5MHz DSP clock. The sys-
tem clock can be stopped for a system sleep mode by disabling the
VCXO supply power from the CCONT regulator output. The CCONT pro-
vides a 32kHz sleep clock for internal use and to the MAD2, which is used
for the sleep mode timing. The sleep clock is active when there is a bat-
tery voltage available i.e. always when the battery is connected.
clock for the DSP, where it is multiplied to 45.5MHz DSP clock. The sys-
tem clock can be stopped for a system sleep mode by disabling the
VCXO supply power from the CCONT regulator output. The CCONT pro-
vides a 32kHz sleep clock for internal use and to the MAD2, which is used
for the sleep mode timing. The sleep clock is active when there is a bat-
tery voltage available i.e. always when the battery is connected.
Figure 22.
MAD
2
A
RCHITECTURE
ARM C
ORE
BUSC
S
YSTEM
L
OGIC
M
C
U
I
F
D
S
P
I
F
UIF
PUP
SIMIF
CTSI
MFI
CODER
ACCIF
SCU
LEAD C
ORE
API
DSP RAM
P
ERIPHERALS
DSP
MCU
DSP
T
EST
I
F
JTAG
JTAG
MAD
2
ICE
C
RUSHER