SMSC LAN9311 User Manual
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
107
Revision 1.4 (08-19-08)
DATASHEET
8.5.4
PIO Reads
PIO reads can be used to access System CSR’s or RX Data and RX/TX Status FIFOs. PIO reads can
be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Read cycle begins when both
nCS and nRD are asserted. Either or both of these control signals must de-assert between cycles for
the period specified in
be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Read cycle begins when both
nCS and nRD are asserted. Either or both of these control signals must de-assert between cycles for
the period specified in
. The cycle ends when
either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.
Read data is valid as indicated in the functional timing diagram in
Read data is valid as indicated in the functional timing diagram in
The endian select signal (END_SEL) has the same timing characteristics as the address lines.
Please refer to
for the AC timing specifications
for PIO read operations.
Note:
Some registers have restrictions on the timing of back-to-back write-read cycles. Please refer
to
to
for information on these restrictions.
Figure 8.3 Functional Timing for PIO Read Operation
VALID
VALID
D[15:0] (OUTPUT)
nCS, nRD
A[x:1]
VALID
END_SEL