SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

144

SMSC LAN9311/LAN9311i

 

Sequential reads are used by the EEPROM Loader. Refer to 

 for

additional information.

For a register level description of a read operation, refer to 

Following the device addressing, a data byte may be written to the EEPROM by outputting the data
after receiving the acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM
slave and the I

2

C master finishes the write cycle with a stop condition. If the EEPROM slave fails to

send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the 

 is set. 

Following the data byte write cycle, the I

2

C master will poll the EEPROM to determine when the byte

write is finished. A start condition is sent followed by a control byte with a control code of 1010b,
chip/block select bits low, and the R/~W bit low. If the EEPROM is finished with the byte write, it will
respond with an acknowledge. Otherwise, it will respond with a no-acknowledge and the I

2

C master

will repeat the poll. If the acknowledge does not occur within 30mS, a time-out occurs. Once the I

2

C

master receives the acknowledge, it concludes by sending a start condition, followed by a stop
condition, which will place the EEPROM into standby.

 illustrates typical I

2

C EEPROM byte write.

For a register level description of a write operation, refer to 

A
C
K

Data Byte

P

A
C
K

S 1 0 1 0

0

Control Byte

0 0 0

S 1 0 1 0

0

0 0 0

S 1 0 1 0

0

0 0 0

...

D
7

D
6

D
5

D
4

D

3

D

2

D
1

D
0

A
C
K

A
C
K

A
C
K

S P

Poll Cycle

Poll Cycle

Poll Cycle

Data Cycle

Conclude

R/~W

Chip / Block 

Select Bits 

R/~W

Chip / Block 

Select Bits 

R/~W

Chip / Block 

Select Bits 

Control Byte

Control Byte