SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

165

Revision 1.4 (08-19-08)

 

GPIO_INT_POL[9:8] bits also determine the polarity of the clock events as described in

. 

In addition to the standard GPIO interrupts in the 

, the IEEE 1588 timestamp enabled GPIO[9:8] pins contain the ability

to generate and clear specific IEEE 1588 related interrupts. When GPIO 9 or GPIO 8 are enabled as
inputs and an active edge occurs, the IEEE 1588 clock capture is indicated by the 1588_GPIO9_INT
and 1588_GPIO8_INT interrupts respectively in the 

. These interrupts are enabled by setting the corresponding 1588_GPIO9_EN

and 1588_GPIO8_EN bits in the 

GPIO inputs must be active for greater than 40nS to be recognized as capture events.

When GPIO 8 and GPIO 9 are enabled, the 1588 Timer Interrupt bit (1588_TIMER_INT) of the 

 can be cleared by an active edge on

GPIO[9:8]. A clear is only registered when the GPIO input is active for greater than 40nS.

Eight pins, GPIO[7:0], are shared with LED functions (nP1LED[3:0] and nP2LED[3:0]). These pins are
configured as LED outputs by setting the corresponding LED_EN bit in the 

. When configured as a LED, the pin is an open-drain, active-low output and the GPIO

related input buffer and pull-up are disabled. The LED outputs are always active low. As a result, a
low signal on the LED pin equates to the LED “on”, and a high signal equates to the LED “off”.

The functions associated with each LED pin are configurable via the LED_FUN[1:0] bits of the 

. These bits allow the configuration of each LED pin to indicate

various port related functions. These functions are described in 

 followed by a detailed

definition of each indication type.

The default values of the LED_FUN[1:0] and LED_EN[7:0] bits of the 

 are determined by the LED_fun_strap[1:0] and LED_en_strap[7:0] configuration straps.

For more information on the 

 and its related straps, refer to

RX

Port 0

RX

Port 0

Activity

Port 2

-

Link / Activity

Port 2

100Link / Activity

Port 2

Link

Port 2

-

Full-duplex / Collision

Port 2

Full-duplex / Collision

Port 2

Full-duplex / Collision

Port 2

TXEN

Port 2

Speed

Port 2

10Link / Activity

Port 2

Speed

Port 2

RXDV
Port 2

TX

Port 0

TX

Port 0

Activity

Port 1

TXEN

Port 0

Link / Activity

Port 1

100Link / Activity

Port 1

Link

Port 1

RXDV
Port 0