SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

52

SMSC LAN9311/LAN9311i

 

The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The top-level PHY_INT1
(bit 26) and PHY_INT2 (bit 27) of the 

 provides indication that a

P H Y   i n t e r r u p t   e v e n t   o c c u r r e d   i n   t h e  

Port 1 and Port 2 PHY interrupts are enabled/disabled via their respective 

. The source of a PHY interrupt can be determined and cleared

. The Port 1 and

Port 2 PHYs are each capable of generating unique interrupts based on the following events:

„

ENERGYON Activated

„

Auto-Negotiation Complete

„

Remote Fault Detected

„

Link Down (Link Status Negated)

„

Auto-Negotiation LP Acknowledge

„

Parallel Detection Fault

„

Auto-Negotiation Page Received

In order for a Port 1 or Port 2 interrupt event to trigger the external IRQ interrupt pin, the desired PHY
interrupt event must be enabled in the corresponding 

, the PHY_INT1(Port 1 PHY) and/or PHY_INT2(Port 2 PHY) bits of the

 must be set, and IRQ output must be enabled via bit 8 (IRQ_EN)

For additional details on the Ethernet PHY interrupts, refer to 

Each GPIO[11:0] of the LAN9311/LAN9311i is provided with its own interrupt. The top-level GPIO (bit
12) of the 

 provides indication that a GPIO interrupt event occurred

in the 

 provides enabling/disabling

and status of each GPIO[11:0] interrupt.

In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt
m u s t   b e   e n a b l e d  i n  t h e  

, bit 12 (GPIO_EN) of the 

 must be set, and

IRQ output must be enabled via bit 8 (IRQ_EN) of the 

For additional details on the GPIO interrupts, refer to 

.

The top-level 

, and 

 provide the

status and enabling/disabling of multiple Host MAC related interrupts. All Host MAC interrupts are
monitored and configured directly within these two registers. The following Host MAC related interrupt
events are supported:

„

TX Stopped

„

RX Stopped

„

RX Dropped Frame Counter Halfway

„

TX IOC

„

RX DMA