SMSC flexpwr lan8710 User Manual

MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR

® 

 Technology in a Small Footprint

SMSC LAN8710/LAN8710i

19

Revision 1.0 (04-15-09)

Functionally, the transceiver can be divided into the following sections:

„

100Base-TX transmit and receive

„

10Base-T transmit and receive

„

MII or RMII interface to the controller

„

Auto-negotiation to automatically determine the best speed and duplex possible

„

Management Control to read status registers and write control registers

The data path of the 100Base-TX is shown in 

. Each major block is explained below.

For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s MII block on the rising edge of TXCLK. The data
is in the form of 4-bit wide 25MHz data. 

For RMII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The
data is in the form of 2-bit wide 50MHz data. 

M A C

T x 

D river

M LT -3 

C onverter

N R Z I 

C onverter

4B /5B  

E ncoder

C A T-5

R J45

25M H z by

5 bits

N R Z I

M LT-3

M LT -3

M LT -3

S cram bler 

and  P IS O

M II/R M II

25M H z

by 4  bits

E xt R ef_C LK  (for R M II only)

P LL

M II 25 M hz by 4 bits

or

R M II 50 M hz by 2 bits

M LT -3

M agnetics

125 M bps S erial

T X _C LK

(for M II only)