Intel Pentium 4 672 HH80547PG1122MH User Manual

                                               

   

11

 

Most system bus signals of the Intel

®

 Pentium

®

 4 Processor in the 423-pin Package system bus 

signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the Intel 
P6 family of microprocessors, this signalling technology provides improved noise margins and 
reduced ringing through low voltage swings and controlled edge rates. Unlike the P6 processor 
family, the termination voltage level for the Pentium 4 processor AGTL+ signals is V

CC

, the 

operating voltage of the processor core. P6 family processors utilize a fixed 1.5V termination 
voltage known as V

TT

. Because of the speed improvements to data and address busses, signal 

integrity and platform design methods become more critical than with previous processor families. 
Design guidelines for the Pentium 4 processor system bus are detailed in the Intel

 850 Chipset Platform Design Guide.

The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to 
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board 
(See Table 13 for GTLREF specifications). Termination resistors are provided on the processor 
silicon and are terminated to its core voltage (V

CC

). Intel chipsets will also provide on-die 

termination, thus eliminating the need to terminate the bus on the system board for most AGTL+ 
signals. 

Some AGTL+ signals do not include on-die termination and must be terminated on the system 
board. See Table 4 for details regarding these signals.

The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+ 
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the 
system bus, including trace lengths, is highly recommended when designing a system. Contact 
your Intel Field Representative to obtain the buffer models, Intel

For clean on-chip power distribution, Pentium 4 processors have 111 V

CC

 (power) and 112 V

SS 

(ground) inputs. All power pins must be connected to V

CC

, while all V

SS

 pins must be connected to 

a system ground plane.The processor V

CC

 pins must be supplied the voltage determined by the VID 

(Voltage ID) pins.

Due to its large number of transistors and high internal clock speeds, the processor is capable of 
generating large average current swings between low and full power states. This may cause 
voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. 
Care must be taken in the board design to ensure that the voltage provided to the processor remains 
within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced 
lifetime of the component. For further information and design guidelines, refer to the Intel

 850 Chipset Platform Design Guide.