Intel Pentium 4 672 HH80547PG1122MH User Manual
Product codes
HH80547PG1122MH
Intel
®
Pentium
®
4 Processor in the 423-pin Package
12
2.3.1
V
CC
Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep a low interconnect resistance from the regulator (or VRM pins) to the socket. Bulk
decoupling for the large current swings when the part is powering on, or entering/exiting low
power states, must be provided by the voltage regulator solution (VRM). For more details on this
topic, refer to the Intel
and keep a low interconnect resistance from the regulator (or VRM pins) to the socket. Bulk
decoupling for the large current swings when the part is powering on, or entering/exiting low
power states, must be provided by the voltage regulator solution (VRM). For more details on this
topic, refer to the Intel
®
Pentium
®
4 Processor and Intel
®
850 Chipset Platform Design Guide.
2.3.2
System Bus AGTL+ Decoupling
Pentium 4 processors integrate signal termination on the die as well as incorporate high frequency
decoupling capacitance on the processor package. Decoupling must also be provided by the system
motherboard for proper AGTL+ bus operation. For more information, refer to the Intel
decoupling capacitance on the processor package. Decoupling must also be provided by the system
motherboard for proper AGTL+ bus operation. For more information, refer to the Intel
®
Pentium
®
4 Processor and Intel
®
850 Chipset Platform Design Guide.
2.3.3
System Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the Pentium 4 processor core frequency is a
multiple of the BCLK[1:0] frequency. The Pentium 4 processor bus ratio multiplier is set at its
default ratio at manufacturing. No jumpers or user intervention is necessary, the processor will
automatically run at the speed indicated on the package.
processor. As in previous generation processors, the Pentium 4 processor core frequency is a
multiple of the BCLK[1:0] frequency. The Pentium 4 processor bus ratio multiplier is set at its
default ratio at manufacturing. No jumpers or user intervention is necessary, the processor will
automatically run at the speed indicated on the package.
Unlike previous processors, the Pentium 4 processor uses a differential clocking implementation.
For more information on Pentium 4 processor clocking, refer to the CK00 Clock Synthesizer/Driver
Design Guidelines.
For more information on Pentium 4 processor clocking, refer to the CK00 Clock Synthesizer/Driver
Design Guidelines.
2.4
Voltage Identification
The VID specification for Pentium 4 processors is different from that of previous generations and
is supported by the VRM 9.0 DC-DC Convertor Design Guidelines. The voltage set by the VID
pins is the maximum voltage allowed by the processor. A minimum voltage is provided in Table 5
and changes with frequency. This allows processors running at a higher frequency to have a relaxed
minimum voltage specification. The specifications have been set such that one voltage regulator
can work with all supported frequencies.
is supported by the VRM 9.0 DC-DC Convertor Design Guidelines. The voltage set by the VID
pins is the maximum voltage allowed by the processor. A minimum voltage is provided in Table 5
and changes with frequency. This allows processors running at a higher frequency to have a relaxed
minimum voltage specification. The specifications have been set such that one voltage regulator
can work with all supported frequencies.
Pentium 4 processors use five voltage identification pins, VID[4:0], to support automatic selection
of power supply voltages. Table 2 specifies the voltage level corresponding to the state of
VID[4:0]. A ‘1’ in this table refers to an open pin and a ‘0’ refers to low voltage level. The
definition provided in Table 2 is not related in any way to previous processors or VRMs. If the
processor socket is empty (VID[4:0] = 11111), or the voltage regulation circuit cannot supply the
voltage that is requested, it must disable itself. See the VRM 9.0 DC/DC Converter Design
Guidelines for more details.
of power supply voltages. Table 2 specifies the voltage level corresponding to the state of
VID[4:0]. A ‘1’ in this table refers to an open pin and a ‘0’ refers to low voltage level. The
definition provided in Table 2 is not related in any way to previous processors or VRMs. If the
processor socket is empty (VID[4:0] = 11111), or the voltage regulation circuit cannot supply the
voltage that is requested, it must disable itself. See the VRM 9.0 DC/DC Converter Design
Guidelines for more details.
Power source characteristics must be guaranteed to be stable whenever the supply to the voltage
regulator is stable.
regulator is stable.