Intel Pentium 4 672 HH80547PG1122MH User Manual
Product codes
HH80547PG1122MH
Intel
®
Pentium
®
4 Processor in the 423-pin Package
25
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at GTLREF at the processor pins. All TAP
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at GTLREF at the processor pins. All TAP
signal timings (TMS, TDI, etc) are referenced at GTLREF at the processor pins.
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
5. Referenced to the falling edge of TCK.
6. Referenced to the rising edge of FBO (TCK) at the debug port connector.
7. TRST# is synchronized to TCK and is asserted for 5 TCK periods while TMS is asserted.
8. Specification for a minimum swing defined between TAP V
5. Referenced to the falling edge of TCK.
6. Referenced to the rising edge of FBO (TCK) at the debug port connector.
7. TRST# is synchronized to TCK and is asserted for 5 TCK periods while TMS is asserted.
8. Specification for a minimum swing defined between TAP V
IL_MAX
to V
IH_MIN
. This assumes a minimum edge
rate of 0.5V/ns.
2.13
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 10 through Table
15.
15.
Note: For Figure 4 through Figure 11, the following apply:
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage
(V
(V
CROSS
) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings
are referenced at GTLREF at the processor core.
2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe
(address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge of
their associated data strobe. Source synchronous address signals are referenced to the rising and
falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are
referenced at GTLREF at the processor silicon.
(address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge of
their associated data strobe. Source synchronous address signals are referenced to the rising and
falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are
referenced at GTLREF at the processor silicon.
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V
CROSS
. All AGTL+
strobe signal timings are referenced at GTLREF at the processor silicon.
4. All AC timings for the TAP signals are referenced to the TCK signal at GTLREF at the processor
pins. All TAP signal timings (TMS, TDI, etc) are referenced at the processor pins.
pins. All TAP signal timings (TMS, TDI, etc) are referenced at the processor pins.
The circuit used to test the AC specifications is shown in Figure 3.
Table 15. TAP Signals AC Specifications
Parameter
Min
Max
Unit
Figure
Notes
1,2,3
T55: TCK Period
60.0
1000
ns
T56: TCK Rise Time
9.5
ns
4
T57: TCK Fall Time
9.5
ns
4
T58: TMS Rise Time
8.5
ns
4
T59: TMS Fall Time
8.5
ns
4
T60: TMS Clock to Output Delay
-5
-2
ns
5
T61: TDI Setup Time
0
ns
5, 8
T62: TDI Hold Time
3
ns
5, 8
T63: TDO Clock to Output Delay
0.5
3.5
ns
6
T64: TRST# Assert Time
2
TCK
7