Intel Pentium 4 672 HH80547PG1122MH User Manual
Product codes
HH80547PG1122MH
Intel
®
Pentium
®
4 Processor in the 423-pin Package
27
.
Figure 5. Differential Clock Waveform
Figure 6. System Bus Common Clock Valid Delay Timings
Crossing
Voltage
Threshold
Region
VH
VL
Overshoot
Undershoot
Ringback
Margin
Rising Edge
Ringback
Falling Edge
Ringback,
BCLK0
BCLK1
Crossing
Voltage
Tph
Tpl
Tp
Tp = T1 (BCLK[1:0] period)
T2 = BCLK[1:0] Period stability (not shown)
Tph =T3 (BCLK[1:0] pulse high time)
Tpl = T4 (BCLK[1:0] pulse low time)
T5 = BCLK[1:0] rise time through the threshold region (not shown)
T6 = BCLK[1:0] fall time through the threshold region (not shown)
T2 = BCLK[1:0] Period stability (not shown)
Tph =T3 (BCLK[1:0] pulse high time)
Tpl = T4 (BCLK[1:0] pulse low time)
T5 = BCLK[1:0] rise time through the threshold region (not shown)
T6 = BCLK[1:0] fall time through the threshold region (not shown)
BCLK0
BCLK1
Common Clock
Signal (@ driver)
Common Clock
Signal (@ receiver)
T0
T1
T2
T
Q
T
R
valid
valid
valid
T
P
T
P
= T10: T
CO
(Data Valid Output Delay)
T
Q
= T11: T
SU
(Common Clock Setup)
T
R
= T12: T
H
(Common Clock Hold Time)