Intel Pentium 4 672 HH80547PG1122MH User Manual
Product codes
HH80547PG1122MH
Intel
®
Pentium
®
4 Processor in the 423-pin Package
29
Figure 9. Source Synchronous 4X Timings
Figure 10. Power-On Reset and Configuration Timings
BCLK0
BCLK1
DSTBp# (@ driver)
DSTBn# (@ driver)
D# (@ driver)
D# (@ receiver)
DSTBn# (@ receiver)
DSTBp# (@ receiver)
T0
T1
T2
2.5 ns
5.0 ns
7.5 ns
T
A
T
A
T
B
T
C
T
E
T
E
T
G
T
G
T
D
T
A
= T21: Source Sync. Data Output Valid Delay Before Data Strobe
T
B
= T22: Source Sync. Data Output Valid Delay After Data Strobe
T
C
= T27: Source Sync. Setup Time to BCLK
T
D
= T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay
T
E
= T25: Source Sync. Input Setup Time
T
G
= T26: Source Sync. Input Hold Time
T
H
= T29: First Data Strobe to Subsequent Strobes
T
J
= T20: Source Sync. Data Output Valid Delay
T
J
T
H
Valid Ratio
T
a
BCLK
V
CC
, core,
V
REF
Configuration
(A20M#, IGNNE#,
LINT[1:0])
T
a
= T15 (PWRGOOD Inactive Pulse Width)
T
b
= T10 (RESET# Pulse Width)
T
c
= T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
T
b
T
c
PWRGOOD
RESET#
Vcc
Ta = T37 (PWRGOOD Inactive Pulse Width)
Tb = T36 (PWRGOOD to RESET# de-assertion time)
Tc = T46 (Reset Configuration Signals Hold Time)
Tb = T36 (PWRGOOD to RESET# de-assertion time)
Tc = T46 (Reset Configuration Signals Hold Time)