Intel i5-2400 BX80623I52400 User Manual
Product codes
BX80623I52400
Power Management
52
Datasheet, Volume 1
4.3
IMC Power Management
The main memory is power managed during normal operation and in low-power ACPI
Cx states.
Cx states.
4.3.1
Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as DIMM connector is
unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM
signals are:
which it is not connected to any actual memory devices (such as DIMM connector is
unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM
signals are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with an SO-DIMM
present, the DIMM is not ensured to maintain data integrity.
not populated. This is due to the fact that when CKE is tristated with an SO-DIMM
present, the DIMM is not ensured to maintain data integrity.
SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
must be assumed to be populated.
4.3.2
DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals that the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals that the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
The CKE is one of the power-save means. When CKE is off the internal DDR clock is
disabled and the DDR power is reduced. The power-saving differs according the
selected mode and the DDR type used. For more information, please refer to the IDD
table in the DDR specification.
The DDR specification defines 3 levels of power-down that differ in power-saving and in
wakeup time:
1. Active power-down (APD): This mode is entered if there are open pages when de-
asserting CKE. In this mode the open pages are retained. Power-saving in this
mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this
mode is fined by tXP – small number of cycles.
mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this
mode is fined by tXP – small number of cycles.
2. Precharged power-down (PPD): This mode is entered if all banks in DDR are
precharged when de-asserting CKE. Power-saving in this mode is intermediate –
better than APD, but less than DLL-off. Power consumption is defined by IDD2P1.
Exiting this mode is defined by tXP. Difference from APD mode is that when waking-
up all page-buffers are empty
better than APD, but less than DLL-off. Power consumption is defined by IDD2P1.
Exiting this mode is defined by tXP. Difference from APD mode is that when waking-
up all page-buffers are empty
3. DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this mode is
the best among all power-modes. Power consumption is defined by IDD2P1. Exiting
this mode is defined by tXP, but also tXPDLL (10 – 20 according to DDR type) cycles
until first data transfer is allowed.
this mode is defined by tXP, but also tXPDLL (10 – 20 according to DDR type) cycles
until first data transfer is allowed.