Intel i5-2400 User Manuals

Table of Contents

• 2nd Generation Intel® Core™ Processor Family Desktop

  1
• Contents

  3
• Tables

  7
• Revision History

  8
• 1 Introduction

  9
  • 1.1 Processor Feature Details

    11
    • 1.1.1 Supported Technologies

      11
  • 1.2 Interfaces

    11
    • 1.2.1 System Memory Support

      11
    • 1.2.2 PCI Express*

      12
    • 1.2.3 Direct Media Interface (DMI)

      13
    • 1.2.4 Platform Environment Control Interface (PECI)

      14
    • 1.2.5 Processor Graphics

      14
    • 1.2.6 Intel® Flexible Display Interface (Intel® FDI)

      14
  • 1.3 Power Management Support

    15
    • 1.3.1 Processor Core

      15
    • 1.3.2 System

      15
    • 1.3.3 Memory Controller

      15
    • 1.3.4 PCI Express*

      15
    • 1.3.5 DMI

      15
    • 1.3.6 Processor Graphics Controller

      15
  • 1.4 Thermal Management Support

    15
  • 1.5 Package

    16
  • 1.6 Terminology

    16
  • 1.7 Related Documents

    18
• 2 Interfaces

  19
  • 2.1 System Memory Interface

    19
    • 2.1.1 System Memory Technology Supported

      19
    • 2.1.2 System Memory Timing Support

      20
    • 2.1.3 System Memory Organization Modes

      21
      • 2.1.3.1 Single-Channel Mode

        21
      • 2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

        21
    • 2.1.4 Rules for Populating Memory Slots

      22
    • 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

      22
      • 2.1.5.1 Just-in-Time Command Scheduling

        22
      • 2.1.5.2 Command Overlap

        23
      • 2.1.5.3 Out-of-Order Scheduling

        23
    • 2.1.6 Memory Type Range Registers (MTRRs) Enhancement

      23
    • 2.1.7 Data Scrambling

      23
  • 2.2 PCI Express* Interface

    24
    • 2.2.1 PCI Express* Architecture

      24
      • 2.2.1.1 Transaction Layer

        25
      • 2.2.1.2 Data Link Layer

        25
      • 2.2.1.3 Physical Layer

        25
    • 2.2.2 PCI Express* Configuration Mechanism

      26
    • 2.2.3 PCI Express* Port

      26
    • 2.2.4 PCI Express Lanes Connection

      27
  • 2.3 Direct Media Interface (DMI)

    27
    • 2.3.1 DMI Error Flow

      27
    • 2.3.2 Processor/PCH Compatibility Assumptions

      27
    • 2.3.3 DMI Link Down

      28
  • 2.4 Processor Graphics Controller (GT)

    28
    • 2.4.1 3D and Video Engines for Graphics Processing

      29
      • 2.4.1.1 3D Engine Execution Units

        29
      • 2.4.1.2 3D Pipeline

        29
      • 2.4.1.3 Video Engine

        30
      • 2.4.1.4 2D Engine

        30
    • 2.4.2 Processor Graphics Display

      31
      • 2.4.2.1 Display Planes

        31
      • 2.4.2.2 Display Pipes

        32
      • 2.4.2.3 Display Ports

        32
    • 2.4.3 Intel Flexible Display Interface

      32
    • 2.4.4 Multi-Graphics Controller Multi-Monitor Support

      32
  • 2.5 Platform Environment Control Interface (PECI)

    33
  • 2.6 Interface Clocking

    33
    • 2.6.1 Internal Clocking Requirements

      33
• 3 Technologies

  35
  • 3.1 Intel® Virtualization Technology

    35
    • 3.1.1 Intel® VT-x Objectives

      35
    • 3.1.2 Intel® VT-x Features

      36
    • 3.1.3 Intel® VT-d Objectives

      36
    • 3.1.4 Intel® VT-d Features

      37
    • 3.1.5 Intel® VT-d Features Not Supported

      37
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    38
  • 3.3 Intel® Hyper-Threading Technology

    38
  • 3.4 Intel® Turbo Boost Technology

    39
    • 3.4.1 Intel® Turbo Boost Technology Frequency

      39
    • 3.4.2 Intel® Turbo Boost Technology Graphics Frequency

      39
  • 3.5 Intel® Advanced Vector Extensions (AVX)

    40
  • 3.6 Advanced Encryption Standard New Instructions (AES-NI)

    40
    • 3.6.1 PCLMULQDQ Instruction

      40
  • 3.7 Intel® 64 Architecture x2APIC

    41
• 4 Power Management

  43
  • 4.1 ACPI States Supported

    43
    • 4.1.1 System States

      43
    • 4.1.2 Processor Core/Package Idle States

      43
    • 4.1.3 Integrated Memory Controller States

      44
    • 4.1.4 PCIe Link States

      44
    • 4.1.5 DMI States

      44
    • 4.1.6 Processor Graphics Controller States

      44
    • 4.1.7 Interface State Combinations

      45
  • 4.2 Processor Core Power Management

    45
    • 4.2.1 Enhanced Intel® SpeedStep® Technology

      45
    • 4.2.2 Low-Power Idle States

      46
    • 4.2.3 Requesting Low-Power Idle States

      47
    • 4.2.4 Core C-states

      48
      • 4.2.4.1 Core C0 State

        48
      • 4.2.4.2 Core C1/C1E State

        48
      • 4.2.4.3 Core C3 State

        48
      • 4.2.4.4 Core C6 State

        48
      • 4.2.4.5 C-State Auto-Demotion

        48
    • 4.2.5 Package C-States

      49
      • 4.2.5.1 Package C0

        50
      • 4.2.5.2 Package C1/C1E

        51
      • 4.2.5.3 Package C3 State

        51
      • 4.2.5.4 Package C6 State

        51
  • 4.3 IMC Power Management

    52
    • 4.3.1 Disabling Unused System Memory Outputs

      52
    • 4.3.2 DRAM Power Management and Initialization

      52
      • 4.3.2.1 Initialization Role of CKE

        54
      • 4.3.2.2 Conditional Self-Refresh

        54
      • 4.3.2.3 Dynamic Power-down Operation

        54
      • 4.3.2.4 DRAM I/O Power Management

        54
  • 4.4 PCIe* Power Management

    54
  • 4.5 DMI Power Management

    55
  • 4.6 Graphics Power Management

    55
    • 4.6.1 Intel® Rapid Memory Power Management (RMPM) (also know as CxSR)

      55
    • 4.6.2 Intel® Graphics Performance Modulation Technology(GPMT)

      55
    • 4.6.3 Graphics Render C-State

      55
    • 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)

      55
    • 4.6.5 Intel® Graphics Dynamic Frequency

      56
  • 4.7 Thermal Power Management

    56
• 5 Thermal Management

  57
• 6 Signal Description

  59
  • 6.1 System Memory Interface

    60
  • 6.2 Memory Reference and Compensation

    61
  • 6.3 Reset and Miscellaneous Signals

    62
  • 6.4 PCI Express* Based Interface Signals

    63
  • 6.5 Intel® Flexible Display Interface Signals

    63
  • 6.6 DMI

    64
  • 6.7 PLL Signals

    64
  • 6.8 TAP Signals

    64
  • 6.9 Error and Thermal Protection

    65
  • 6.10 Power Sequencing

    65
  • 6.11 Processor Power Signals

    66
  • 6.12 Sense Pins

    66
  • 6.13 Ground and NCTF

    66
  • 6.14 Processor Internal Pull Up/Pull Down

    67
• 7 Electrical Specifications

  69
  • 7.1 Power and Ground Lands

    69
  • 7.2 Decoupling Guidelines

    69
    • 7.2.1 Voltage Rail Decoupling

      69
  • 7.3 Processor Clocking (BCLK[0], BCLK#[0])

    70
    • 7.3.1 PLL Power Supply

      70
  • 7.4 VCC Voltage Identification (VID)

    70
  • 7.5 System Agent (SA) VCC VID

    74
  • 7.6 Reserved or Unused Signals

    74
  • 7.7 Signal Groups

    75
  • 7.8 Test Access Port (TAP) Connection

    76
  • 7.9 Storage Conditions Specifications

    77
  • 7.10 DC Specifications

    78
    • 7.10.1 Voltage and Current Specifications

      78
  • 7.11 Platform Environmental Control Interface (PECI) DC Specifications

    84
    • 7.11.1 PECI Bus Architecture

      84
    • 7.11.2 DC Characteristics

      85
    • 7.11.3 Input Device Hysteresis

      85
• 8 Processor Pin and Signal Information

  87
  • 8.1 Processor Pin Assignments

    87
• 9 DDR Data Swizzling

  107