Intel 41210 User Manual

26

In summary:

•

A_RST# and B_RST# are outputs from the 41210.

•

PCI clocks are actively driven out from the 41210.

•

The 41210 drives X_AD[31:0], X_BE[3:0], and X_PAR low during PCI bus reset.

•

The 41210 drives X_REQ64# low during reset.

 lists all the transactions supported by the 41210 on the PCI bus. The 41210 supports full 

64-bit addressing upstream and downstream and can both generate and accept dual address cycles.

Interrupt acknowledge

0000

No

No

Special cycle (PCI Express* Type1-to-PCI Special 
Cycle)

0001

Yes

No

I/O read

0010

Yes

Yes

I/O write

0011

Yes

Yes

Memory read

0110

Yes

Yes

Memory write

0111

Yes

Yes

Configuration read

1010

Yes

Yes

Configuration write

1011

Yes

Yes

Memory read multiple

1100

No

Yes

Dual address cycle

1101

Yes

Yes

Memory read line

1110

No

Yes

Memory write and invalidate

1111

No

Yes

LOCK transaction

–

Yes

No

1. PCI command encodings that are not shown in this table are ignored.
2. I/O transactions are forwarded from PCI to PCI Express* only when the inbound I/O enable bit is set in the 

3. Upstream Type 0 configuration cycles to the 41210 Bridge’s own configuration space are supported.