Intel 41210 User Manual
56
Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
System Management Bus Interface
8.1
SMBus Commands
The 41210 supports six SMBus commands:
Sequencing these commands initiates accesses to the internal configuration and memory registers.
For high reliability, the 41210 also supports the optional packet-error-checking feature (CRC-8)
and is enabled or disabled with each transaction.
For high reliability, the 41210 also supports the optional packet-error-checking feature (CRC-8)
and is enabled or disabled with each transaction.
Every configuration and memory read or write consists first of an SMBus write sequence that
initializes the bus number, device, function number, register offset, and so on. The term sequence is
used because these variables can be initialized by the SMBus master with a single block write or
multiple word or byte writes. The last write in the sequence that completes the initialization
performs the internal configuration/memory read or write. The SMBus master can then initiate a
read sequence, which returns the status of the internal read or write command and also the data in
case of a read.
initializes the bus number, device, function number, register offset, and so on. The term sequence is
used because these variables can be initialized by the SMBus master with a single block write or
multiple word or byte writes. The last write in the sequence that completes the initialization
performs the internal configuration/memory read or write. The SMBus master can then initiate a
read sequence, which returns the status of the internal read or write command and also the data in
case of a read.
Each SMBus transaction has an 8-bit command driven by the master. The command encodes the
information shown in
information shown in
:
•
Block Write
•
Word Write
•
Byte Write
•
Block Read
•
Word Read
•
Byte Read
Table 26.
SMBus Command Encoding
Bit
Description
7
Begin:
When set, this bit indicates the first transaction of the read or write sequence.
6
End:
When set, this bit indicates the last transaction of the read or write sequence.
5
Reserved:
Must be set to 0.
4
PEC Enable:
When set, indicates that PEC is enabled. When set, each transaction in the sequence
ends with an extra CRC byte. CRC is checked on writes and generated on reads.
PEC does not include the command byte itself.
3:2
Internal Command:
00 Read Dword
01 Write Byte
10 Write Word
11 Write Dword
01 Write Byte
10 Write Word
11 Write Dword
All accesses are naturally aligned to the access width. This field specifies the command to be issued
by the SMBus slave logic to the internal registers.
by the SMBus slave logic to the internal registers.
1:0
SMBus command:
00 Byte
01 Word
10 Block
11 Reserved
01 Word
10 Block
11 Reserved
This field specifies the SMBus command to be issued on the SMBus. This field is used as an
indication of the length of transfer so that the slave knows when to expect the PEC packet (when
enabled).
indication of the length of transfer so that the slave knows when to expect the PEC packet (when
enabled).