Intel CM8063501287403 User Manual

 

22

Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families

Datasheet Volume One of Two

Refer to the following documents for additional information.

SKU

A processor Stock Keeping Unit (SKU) to be installed in either server or 

workstation platforms. Electrical, power and thermal specifications for these 

SKU’s are based on specific use condition assumptions. Server processors may 

be further categorized as Efficient Performance server, workstation and HPC 

SKUs. For further details on use condition assumptions, please refer to the latest 

Product Release Qualification (PRQ) Report available via your Customer Quality 

Engineer (CQE) contact.

SMBus

System Management Bus. A two-wire interface through which simple system and 

power management related devices can communicate with the rest of the 

system. It is based on the principals of the operation of the I2C* two-wire serial 

bus from Philips Semiconductor.

Storage Conditions

A non-operational state. The processor may be installed in a platform, in a tray, 

or loose. Processors may be sealed in packaging or exposed to free air. Under 

these conditions, processor landings should not be connected to any supply 

voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” 

(that is, unsealed packaging or a device removed from packaging material) the 

processor must be handled in accordance with moisture sensitivity labeling 

(MSL) as indicated on the packaging material.

TAC

Thermal Averaging Constant

TDP

Thermal Design Power

TSOD

Thermal Sensor on DIMM

UDIMM

Unbuffered Dual In-line Module

Uncore

The portion of the processor comprising the shared cache, IMC, HA, PCU, UBox, 

and Intel QPI link interface.

Unit Interval

Signaling convention that is binary and unidirectional. In this binary signaling, 

one bit is sent for every edge of the forwarded clock, whether it be a rising edge 

or a falling edge. If a number of edges are collected at instances t

1

, t

2

, t

n

,...., t

k

 

then the UI at instance “n” is defined as: 

UI 

n

 

= t 

n

 

- t 

n

 - 1

V

CC

Processor core power supply

V

SS

Processor ground

V

CCD

_01, VCCD_23

Variable power supply for the processor system memory interface. VCCD is the 

generic term for VCCD_01, VCCD_23.

x1

Refers to a Link or Port with one Physical Lane

x4

Refers to a Link or Port with four Physical Lanes

x8

Refers to a Link or Port with eight Physical Lanes

x16

Refers to a Link or Port with sixteen Physical Lanes

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