Intel CM8063501287403 User Manual
Power Management
94
Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families
Datasheet Volume One of Two
4.2.5.3
Package C2 State
Package C2 state is an intermediate state which represents the point at which the
system level coordination is in progress. The package cannot reach this state unless all
system level coordination is in progress. The package cannot reach this state unless all
cores are in at least C3.
The package will remain in C2 when:
• it is awaiting for a coordinated response
• the coordinated exit latency requirements are too stringent for the package to take
• the coordinated exit latency requirements are too stringent for the package to take
any power saving actions
If the exit latency requirements are high enough the package will transition to C3 or C6
depending on the state of the cores.
4.2.5.4
Package C3 State
A processor enters the package C3 low power state when:
• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been
• The other cores are in a C3 or lower power state, and the processor has been
granted permission by the platform.
• L3 shared cache retains context and becomes inaccessible in this state.
• Additional power savings actions, as allowed by the exit latency requirements,
• Additional power savings actions, as allowed by the exit latency requirements,
include putting Intel QPI and PCIe* links in L1, the uncore is not available, further
voltage reduction can be taken.
In package C3, the ring will be off and as a result no accesses to the LLC are possible.
The content of the LLC is preserved.
4.2.5.5
Package C6 State
A processor enters the package C6 low power state when:
• At least one core is in the C6 state.
• The other cores are in a C6 or lower power state, and the processor has been
• The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform.
• L3 shared cache retains context and becomes inaccessible in this state.
• Additional power savings actions, as allowed by the exit latency requirements,
• Additional power savings actions, as allowed by the exit latency requirements,
include putting Intel QPI and PCIe* links in L1, the uncore is not available, further
voltage reduction can be taken.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The LLC retains context, but no accesses can be
made to the LLC in this state, the cores must break out to the internal state package C2
for snoops to occur.
for snoops to occur.