Intel CM8063501287403 User Manual

Power Management

Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families

Datasheet Volume One of Two

— The platform may allow additional power savings to be realized in the

processor.

• For package C-states, the processor is not required to enter C0 before entering any

other C-state.

The processor exits a package C-state when a break event is detected. Depending on

the type of break event, the processor does the following:

• If a core break event is received, the target core is activated and the break event

message is forwarded to the target core.

— If the break event is not masked, the target core enters the core C0 state and

the processor enters package C0.

— If the break event is masked, the processor attempts to re-enter its previous

package state.

• If the break event was due to a memory access or snoop request.

— But the platform did not request to keep the processor in a higher package

C-state, the package returns to its previous C-state.

— And the platform requests a higher power C-state, the memory access or snoop

request is serviced and the package remains in the higher power C-state.

The package C-states fall into two categories: independent and coordinated.

C0/C1/C1E are independent, while C2/C3/C6 are coordinated.

Package C-states are based on exit latency requirements which are accumulated from
the PCIe* devices, PCH, and software sources. The level of power savings that can be

achieved is a function of the exit latency requirement from the platform. As a result,

there is no fixed relationship between the coordinated C-state of a package, and the
power savings that will be obtained from the state. Coordinated package C-states offer

a range of power savings which is a function of the guaranteed exit latency requirement

from the platform.

There is also a concept of Execution Allowed (EA), when EA status is 0, the cores in a

socket are in C3 or a deeper state, a socket initiates a request to enter a coordinated

package C-state. The coordination is across all sockets and the PCH.

Table 4-9

shows an example of a dual-core processor package C-state resolution.

Figure 4-3

summarizes package C-state transitions with package C2 as the interim

between PC0 and PC1 prior to PC3 and PC6.

Table 4-9.

Coordination of Core Power States at the Package Level

Package C-State

Core 1

1. The package C-state will be C1E if all actives cores have resolved a core C1 state or higher.