Intel architecture ia-32 User Manual

4-44 Vol. 3A

When execute disable bit capability is enabled (IA32_EFER.NXE = 1), conditions for a page
fault to occur include the same conditions that apply to an IA-32 processor without execute
disable bit capability plus the following new condition: an instruction fetch to a linear address
that translates to physical address in a memory page that has the execute-disable bit set.

An Execute Disable Bit page fault can occur at all privilege levels. It can occur on any instruc-
tion fetch, including (but not limited to): near branches, far branches, CALL/RET/INT/IRET
execution, sequential instruction fetches, and task switches. The execute-disable bit in the page
translation mechanism is checked only when:

•

IA32_EFER.NXE = 1.

•

The instruction translation look-aside buffer (ITLB) is loaded with a page that is not
already present in the ITLB.

32-bit

KByte paging (non-PAE)

 No reserved bits checked

PSE36 - PDE, 4-MByte page

 Bit [21] 

PSE36 - PDE, 4-KByte page

 No reserved bits checked

PSE36 - PTE

 No reserved bits checked

PAE - PDP table entry

 Bits [63:40] & [8:5] & [2:1]

1

 

PAE - PDE, 2-MByte page

 Bits [63:40] & [20:13]

1

 

PAE - PDE, 4-KByte page

 Bits [63:40]

1

 

PAE - PTE

 Bits [63:40]

1

64-bit

PML4E

 Bit [63], bits [51:40] 

PDPTE

 Bit [63], bits [51:40] 

PDE, 2-MByte page

 Bit [63], bits [51:40] & [20:13] 

PDE, 4-KByte page

 Bit [63], bits [51:40] 

PTE

 Bit [63], bits [51:40] 

1. Reserved bit checking also applies to bits 39:36 for processors that support only 36-bits of physical

address. For processor that support only 32 bits of physical address, reserved bit checking also applies
to bits 39:32.