Intel architecture ia-32 User Manual

Vol. 3A 5-11

While priority among these classes listed in Table 5-2 is consistent throughout the architecture,
exceptions within each class are implementation-dependent and may vary from processor to
processor. The processor first services a pending exception or interrupt from the class which has
the highest priority, transferring execution to the first instruction of the handler. Lower priority
exceptions are discarded; lower priority interrupts are held pending. Discarded exceptions are

1 (Highest)

Hardware Reset and Machine Checks
- RESET
- Machine Check

2

Trap on Task Switch
- T flag in TSS is set

3

External Hardware Interventions
- FLUSH
- STOPCLK
- SMI
- INIT

4

Traps on the Previous Instruction
- Breakpoints
- Debug Trap Exceptions (TF flag set or data/I-O breakpoint)

5

Nonmaskable Interrupts (NMI)

 1

6

Maskable Hardware Interrupts 

1

7

Code Breakpoint Fault

8

Faults from Fetching Next Instruction 
- Code-Segment Limit Violation
- Code Page Fault

9

Faults from Decoding the Next Instruction
- Instruction length > 15 bytes 
- Invalid Opcode 
- Coprocessor Not Available

10 (Lowest)

Faults on Executing an Instruction
- Overflow
- Bound error
- Invalid TSS
- Segment Not Present
- Stack fault
- General Protection
- Data Page Fault
- Alignment Check
- x87 FPU Floating-point exception
- SIMD floating-point exception

1. The Intel486

TM

 processor and earlier processors group nonmaskable and maskable interrupts in the

same priority class.