Intel architecture ia-32 User Manual
Vol. 3A 5-19
INTERRUPT AND EXCEPTION HANDLING
5.12.2
Interrupt Tasks
When an exception or interrupt handler is accessed through a task gate in the IDT, a task switch
results. Handling an exception or interrupt with a separate task offers several advantages:
results. Handling an exception or interrupt with a separate task offers several advantages:
•
The entire context of the interrupted program or task is saved automatically.
•
A new TSS permits the handler to use a new privilege level 0 stack when handling the
exception or interrupt. If an exception or interrupt occurs when the current privilege level 0
stack is corrupted, accessing the handler through a task gate can prevent a system crash by
providing the handler with a new privilege level 0 stack.
exception or interrupt. If an exception or interrupt occurs when the current privilege level 0
stack is corrupted, accessing the handler through a task gate can prevent a system crash by
providing the handler with a new privilege level 0 stack.
•
The handler can be further isolated from other tasks by giving it a separate address space.
This is done by giving it a separate LDT.
This is done by giving it a separate LDT.
The disadvantage of handling an interrupt with a separate task is that the amount of machine
state that must be saved on a task switch makes it slower than using an interrupt gate, resulting
in increased interrupt latency.
state that must be saved on a task switch makes it slower than using an interrupt gate, resulting
in increased interrupt latency.
A task gate in the IDT references a TSS descriptor in the GDT (see Figure 5-5). A switch to the
handler task is handled in the same manner as an ordinary task switch (see Section 6.3, “Task
Switching”). The link back to the interrupted task is stored in the previous task link field of the
handler task’s TSS. If an exception caused an error code to be generated, this error code is copied
to the stack of the new task.
handler task is handled in the same manner as an ordinary task switch (see Section 6.3, “Task
Switching”). The link back to the interrupted task is stored in the previous task link field of the
handler task’s TSS. If an exception caused an error code to be generated, this error code is copied
to the stack of the new task.
When exception- or interrupt-handler tasks are used in an operating system, there are actually
two mechanisms that can be used to dispatch tasks: the software scheduler (part of the operating
system) and the hardware scheduler (part of the processor's interrupt mechanism). The software
scheduler needs to accommodate interrupt tasks that may be dispatched when interrupts are
enabled.
two mechanisms that can be used to dispatch tasks: the software scheduler (part of the operating
system) and the hardware scheduler (part of the processor's interrupt mechanism). The software
scheduler needs to accommodate interrupt tasks that may be dispatched when interrupts are
enabled.
NOTE
Because IA-32 architecture tasks are not re-entrant, an interrupt-handler task
must disable interrupts between the time it completes handling the interrupt
and the time it executes the IRET instruction. This action prevents another
interrupt from occurring while the interrupt task’s TSS is still marked busy,
which would cause a general-protection (#GP) exception.
must disable interrupts between the time it completes handling the interrupt
and the time it executes the IRET instruction. This action prevents another
interrupt from occurring while the interrupt task’s TSS is still marked busy,
which would cause a general-protection (#GP) exception.