Intel architecture ia-32 User Manual

7-50 Vol. 3A

PAUSE ;

Short delay

JMP Spin_Lock

Get_Lock:

MOV EAX, 1
XCHG EAX, lockvar ; Try to get lock
CMP EAX, 0  ; Test if successful
JNE Spin_Lock

Critical_Section:

<critical section code>
MOV lockvar, 0
...

Continue:

The spin-wait loop above uses a “test, test-and-set” technique for determining the availability of
the synchronization variable. This technique is recommended when writing spin-wait loops.

In IA-32 processor generations earlier than the Pentium 4 processor, the PAUSE instruction is
treated as a NOP instruction.

An operating system may implement different handlers for different idle states. A typical OS
idle loop on an ACPI-compatible OS is shown in Example 7-5: 

// WorkQueue is a memory location indicating there is a thread 
// ready to run.  A non-zero value for WorkQueue is assumed to
// indicate the presence of work to be scheduled on the processor.
// The idle loop is entered with interrupts disabled.

WHILE (1) {

IF (WorkQueue) THEN {
// Schedule work at WorkQueue.

} ELSE 

{

// No work to do - wait in appropriate C-state handler depending 
// on Idle time accumulated

IF (IdleTime >= IdleTimeThreshhold) THEN {
// Call appropriate C1, C2, C3 state handler, C1 handler 
// shown below

}

}

}
// C1 handler uses a Halt instruction
VOID C1Handler() 
{

STI
HLT

}