Intel architecture ia-32 User Manual
8-2 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Local APICs can receive interrupts from the following sources:
•
Locally connected I/O devices — These interrupts originate as an edge or level asserted
by an I/O device that is connected directly to the processor’s local interrupt pins (LINT0
and LINT1). The I/O devices may also be connected to an 8259-type interrupt controller
that is in turn connected to the processor through one of the local interrupt pins.
by an I/O device that is connected directly to the processor’s local interrupt pins (LINT0
and LINT1). The I/O devices may also be connected to an 8259-type interrupt controller
that is in turn connected to the processor through one of the local interrupt pins.
•
Externally connected I/O devices — These interrupts originate as an edge or level
asserted by an I/O device that is connected to the interrupt input pins of an I/O APIC.
Interrupts are sent as I/O interrupt messages from the I/O APIC to one or more of the
processors in the system.
asserted by an I/O device that is connected to the interrupt input pins of an I/O APIC.
Interrupts are sent as I/O interrupt messages from the I/O APIC to one or more of the
processors in the system.
•
Inter-processor interrupts (IPIs) — An IA-32 processor can use the IPI mechanism to
interrupt another processor or group of processors on the system bus. IPIs are used for
software self-interrupts, interrupt forwarding, or preemptive scheduling.
interrupt another processor or group of processors on the system bus. IPIs are used for
software self-interrupts, interrupt forwarding, or preemptive scheduling.
•
APIC timer generated interrupts — The local APIC timer can be programmed to send a
local interrupt to its associated processor when a programmed count is reached (see
Section 8.5.4, “APIC Timer”).
local interrupt to its associated processor when a programmed count is reached (see
Section 8.5.4, “APIC Timer”).
•
Performance monitoring counter interrupts — P6 family, Pentium 4, and Intel Xeon
processors provide the ability to send an interrupt to its associated processor when a
performance-monitoring counter overflows (see Section 18.13.6.9, “Generating an
Interrupt on Overflow”).
processors provide the ability to send an interrupt to its associated processor when a
performance-monitoring counter overflows (see Section 18.13.6.9, “Generating an
Interrupt on Overflow”).
•
Thermal Sensor interrupts — Pentium 4 and Intel Xeon processors provide the ability to
send an interrupt to themselves when the internal thermal sensor has been tripped (see
Section 13.4.2, “Thermal Monitor”).
send an interrupt to themselves when the internal thermal sensor has been tripped (see
Section 13.4.2, “Thermal Monitor”).
•
APIC internal error interrupts — When an error condition is recognized within the local
APIC (such as an attempt to access an unimplemented register), the APIC can be
programmed to send an interrupt to its associated processor (see Section 8.5.3, “Error
Handling”).
APIC (such as an attempt to access an unimplemented register), the APIC can be
programmed to send an interrupt to its associated processor (see Section 8.5.3, “Error
Handling”).
Of these interrupt sources: the processor’s LINT0 and LINT1 pins, the APIC timer, the perfor-
mance-monitoring counters, the thermal sensor, and the internal APIC error detector are
referred to as local interrupt sources. Upon receiving a signal from a local interrupt source,
the local APIC delivers the interrupt to the processor core using an interrupt delivery protocol
that has been set up through a group of APIC registers called the local vector table or LVT (see
Section 8.5.1, “Local Vector Table”). A separate entry is provided in the local vector table for
each local interrupt source, which allows a specific interrupt delivery protocol to be set up for
each source. For example, if the LINT1 pin is going to be used as an NMI pin, the LINT1 entry
in the local vector table can be set up to deliver an interrupt with vector number 2 (NMI inter-
rupt) to the processor core.
mance-monitoring counters, the thermal sensor, and the internal APIC error detector are
referred to as local interrupt sources. Upon receiving a signal from a local interrupt source,
the local APIC delivers the interrupt to the processor core using an interrupt delivery protocol
that has been set up through a group of APIC registers called the local vector table or LVT (see
Section 8.5.1, “Local Vector Table”). A separate entry is provided in the local vector table for
each local interrupt source, which allows a specific interrupt delivery protocol to be set up for
each source. For example, if the LINT1 pin is going to be used as an NMI pin, the LINT1 entry
in the local vector table can be set up to deliver an interrupt with vector number 2 (NMI inter-
rupt) to the processor core.
The local APIC handles interrupts from the other two interrupt sources (externally connected
I/O devices and IPIs) through its IPI message handling facilities.
I/O devices and IPIs) through its IPI message handling facilities.
A processor can generate IPIs by programming the interrupt command register (ICR) in its local
APIC (see Section 8.6.1, “Interrupt Command Register (ICR)”). The act of writing to the ICR
causes an IPI message to be generated and issued on the system bus (for Pentium 4 and Intel
APIC (see Section 8.6.1, “Interrupt Command Register (ICR)”). The act of writing to the ICR
causes an IPI message to be generated and issued on the system bus (for Pentium 4 and Intel