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Intel architecture ia-32 User Manual

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8-4 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
processors through the local interrupt pins; however, this mechanism is commonly not used in
MP systems.
 
Figure 8-2.  Local APICs and I/O APIC When Intel Xeon Processors Are Used in Multiple-
Processor Systems
 
Figure 8-3.  Local APICs and I/O APIC When P6 Family Processors Are Used in Multiple-
Processor Systems
I/O APIC
External
Interrupts
System Chip Set
Processor System Bus
CPU
Local APIC
Processor #2
CPU
Local APIC
Processor #3
CPU
Local APIC
Processor #1
CPU
Local APIC
Processor #3
Bridge
PCI
IPIs
IPIs
IPIs
Interrupt
Messages
IPIs
Interrupt
Messages
Interrupt
Messages
Interrupt
Messages
Interrupt
Messages
CPU
Local APIC
Processor #2
CPU
Local APIC
Processor #3
CPU
Local APIC
Processor #1
Interrupt
Messages
I/O APIC
External
Interrupts
System Chip Set
3-wire APIC Bus 
CPU
Local APIC
Processor #4
IPIs
IPIs
IPIs
IPIs
Interrupt
Messages
Interrupt
Messages
Interrupt
Messages
Interrupt
Messages