Intel architecture ia-32 User Manual
8-16 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
monitor register and its associated interrupt were introduced in the Pentium 4 and Intel Xeon
processors.
processors.
As shown in Figures 8-8, some of these fields and flags are not available (and reserved) for some
entries.
entries.
Figure 8-8. Local Vector Table (LVT)
31
0
7
Vector
Timer Mode
0: One-shot
1: Periodic
1: Periodic
12
15
16
17
18
Delivery Mode
000: Fixed
000: Fixed
100: NMI
Mask
†
0: Not Masked
1: Masked
1: Masked
Address: FEE0 0350H
Value After Reset: 0001 0000H
Reserved
12
13
15
16
Vector
31
0
7
8
10
Address: FEE0 0360H
Address: FEE0 0370H
Address: FEE0 0370H
Vector
Vector
Error
LINT1
LINT0
Value after Reset: 0001 0000H
Address: FEE0 0320H
111: ExtlNT
All other combinations
are Reserved
are Reserved
Interrupt Input
Pin Polarity
Trigger Mode
0: Edge
0: Edge
1: Level
Remote
IRR
Delivery Status
0: Idle
1: Send Pending
1: Send Pending
Timer
13
11
8
11
14
17
Address: FEE0 0340H
Performance
Vector
Thermal
Vector
Mon. Counters
Sensor
Address: FEE0 0330H
† (Pentium 4 and Intel Xeon processors.) When a
performance monitoring counters interrupt is generated,
the mask bit for its associated LVT entry is set.
the mask bit for its associated LVT entry is set.
010: SMI
101: INIT