Intel architecture ia-32 User Manual

9-18 Vol. 3A

6.

Execute the LTR instruction to load the task register with a segment selector to the initial
protected-mode task or to a writable area of memory that can be used to store TSS
information on a task switch.

7.

After entering protected mode, the segment registers continue to hold the contents they had
in real-address mode. The JMP or CALL instruction in step 4 resets the CS register.
Perform one of the following operations to update the contents of the remaining segment
registers.

— Reload segment registers DS, SS, ES, FS, and GS. If the ES, FS, and/or GS registers

are not going to be used, load them with a null selector.

— Perform a JMP or CALL instruction to a new task, which automatically resets the

values of the segment registers and branches to a new code segment.

8.

Execute the LIDT instruction to load the IDTR register with the address and limit of the
protected-mode IDT.

9.

Execute the STI instruction to enable maskable hardware interrupts and perform the
necessary hardware operation to enable NMI interrupts.

Random failures can occur if other instructions exist between steps 3 and 4 above. Failures will
be readily seen in some situations, such as when instructions that reference memory are inserted
between steps 3 and 4 while in system management mode.

The processor switches from protected mode back to real-address mode if software clears the
PE bit in the CR0 register with a MOV CR0 instruction. A procedure that re-enters real-address
mode should perform the following steps:

1.

Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMI
interrupts can be disabled with external circuitry.

2.

If paging is enabled, perform the following operations:

— Transfer program control to linear addresses that are identity mapped to physical

addresses (that is, linear addresses equal physical addresses).

— Insure that the GDT and IDT are in identity mapped pages.

— Clear the PG bit in the CR0 register.

— Move 0H into the CR3 register to flush the TLB.

3.

Transfer program control to a readable segment that has a limit of 64 KBytes (FFFFH).
This operation loads the CS register with the segment limit required in real-address mode.