Intel architecture ia-32 User Manual
13-4 Vol. 3A
POWER AND THERMAL MANAGEMENT
13.3
MWAIT EXTENSIONS FOR ADVANCED POWER
MANAGEMENT
MANAGEMENT
IA-32 processors may support a number of C-state
1
that reduce power consumption for inactive
states. Intel Core Solo and Intel Core Duo processors support both deeper C-state and MWAIT
extensions that can be used by OS to implement power management policy.
extensions that can be used by OS to implement power management policy.
Software should use CPUID to discover if a target processor supports the enumeration of
MWAIT extensions. If CPUID.05H.ECX[Bit 0] = 1, the target processor supports MWAIT
extensions and their enumeration (see Chapter 3, “Instruction Set Reference, A-M,” of IA-32
Intel® Architecture Software Developer’s Manual, Volume 2A).
MWAIT extensions. If CPUID.05H.ECX[Bit 0] = 1, the target processor supports MWAIT
extensions and their enumeration (see Chapter 3, “Instruction Set Reference, A-M,” of IA-32
Intel® Architecture Software Developer’s Manual, Volume 2A).
If CPUID.05H.ECX[Bit 1] = 1, the target processor supports using interrupts as break-events
for MWAIT, even when interrupts are disabled. Use this feature to measure C-state residency as
follows:
for MWAIT, even when interrupts are disabled. Use this feature to measure C-state residency as
follows:
•
Software can write to bit 0 in the MWAIT Extensions register (ECX) when issuing an
MWAIT to enter into a processor-specific C-state or sub C-state.
MWAIT to enter into a processor-specific C-state or sub C-state.
•
When a processor comes out of an inactive C-state or sub C-state, software can read a
timestamp before an interrupt service routine (ISR) is potentially executed.
timestamp before an interrupt service routine (ISR) is potentially executed.
CPUID.05H.EDX allows software to enumerate processor-specific C-states and sub C-states
available for use with MWAIT extensions. IA-32 processors may support more than one C-state
of a given C-state type. These are called sub C-states. Numerically higher C-state have higher
power savings and latency (upon entering and exiting) than lower-numbered C-state.
available for use with MWAIT extensions. IA-32 processors may support more than one C-state
of a given C-state type. These are called sub C-states. Numerically higher C-state have higher
power savings and latency (upon entering and exiting) than lower-numbered C-state.
At CPL = 0, system software can specify desired C-state and sub C-state by using the MWAIT
hints register (EAX). Processors will not go to C-state and sub C-state deeper than what is spec-
ified by the hint register. If CPL > 0 and if MONITOR/MWAIT is supported at CPL > 0, the
processor will only enter C1-state (regardless of the C-state request in the hints register).
hints register (EAX). Processors will not go to C-state and sub C-state deeper than what is spec-
ified by the hint register. If CPL > 0 and if MONITOR/MWAIT is supported at CPL > 0, the
processor will only enter C1-state (regardless of the C-state request in the hints register).
Executing MWAIT generates an exception on processors operating at a privilege level where
MONITOR/MWAIT are not supported.
MONITOR/MWAIT are not supported.
NOTE
If MWAIT is used to enter a C-state (including sub C-state) that is
numerically higher than C1, a store to the address range armed by MONITOR
instruction will cause the processor to exit MWAIT if the store was originated
by other processor agents. A store from non-processor agent may not cause
the processor to exit MWAIT.
numerically higher than C1, a store to the address range armed by MONITOR
instruction will cause the processor to exit MWAIT if the store was originated
by other processor agents. A store from non-processor agent may not cause
the processor to exit MWAIT.
1. The processor-specific C-state defined in MWAIT extensions can map to ACPI defined C-state types (C0,
C1, C2, C3). The mapping relationship depends on the definition of a C-state by processor implementa-
tion and is exposed to OSPM by the BIOS using the ACPI defined _CST table.
tion and is exposed to OSPM by the BIOS using the ACPI defined _CST table.