Intel architecture ia-32 User Manual
17-40 Vol. 3A
IA-32 ARCHITECTURE COMPATIBILITY
17.36.3 Memory Type Range Registers
Memory type range registers (MTRRs) are a new feature introduced into the IA-32 in the
Pentium Pro processor. MTRRs allow the processor to optimize memory operations for different
types of memory, such as RAM, ROM, frame buffer memory, and memory-mapped I/O.
Pentium Pro processor. MTRRs allow the processor to optimize memory operations for different
types of memory, such as RAM, ROM, frame buffer memory, and memory-mapped I/O.
MTRRs are MSRs that contain an internal map of how physical address ranges are mapped to
various types of memory. The processor uses this internal memory map to determine the cache-
ability of various physical memory locations and the optimal method of accessing memory loca-
tions. For example, if a memory location is specified in an MTRR as write-through memory, the
processor handles accesses to this location as follows. It reads data from that location in lines
and caches the read data or maps all writes to that location to the bus and updates the cache to
maintain cache coherency. In mapping the physical address space with MTRRs, the processor
recognizes five types of memory: uncacheable (UC), uncacheable, speculatable, write-
combining (USWC), write-through (WT), write-protected (WP), and writeback (WB).
various types of memory. The processor uses this internal memory map to determine the cache-
ability of various physical memory locations and the optimal method of accessing memory loca-
tions. For example, if a memory location is specified in an MTRR as write-through memory, the
processor handles accesses to this location as follows. It reads data from that location in lines
and caches the read data or maps all writes to that location to the bus and updates the cache to
maintain cache coherency. In mapping the physical address space with MTRRs, the processor
recognizes five types of memory: uncacheable (UC), uncacheable, speculatable, write-
combining (USWC), write-through (WT), write-protected (WP), and writeback (WB).
Earlier IA-32 processors (such as the Intel486 and Pentium processors) used the KEN# (cache
enable) pin and external logic to maintain an external memory map and signal cacheable
accesses to the processor. The MTRR mechanism simplifies hardware designs by eliminating
the KEN# pin and the external logic required to drive it.
enable) pin and external logic to maintain an external memory map and signal cacheable
accesses to the processor. The MTRR mechanism simplifies hardware designs by eliminating
the KEN# pin and the external logic required to drive it.
See Chapter 9, “Processor Management and Initialization,” and Appendix B, “Model-Specific
Registers (MSRs),” for more information on the MTRRs.
Registers (MSRs),” for more information on the MTRRs.
17.36.4 Machine-Check Exception and Architecture
The Pentium processor introduced a new exception called the machine-check exception (#MC,
interrupt 18). This exception is used to detect hardware-related errors, such as a parity error on
a read cycle.
interrupt 18). This exception is used to detect hardware-related errors, such as a parity error on
a read cycle.
The P6 family processors extend the types of errors that can be detected and that generate a
machine-check exception. It also provides a new machine-check architecture for recording
information about a machine-check error and provides extended recovery capability.
machine-check exception. It also provides a new machine-check architecture for recording
information about a machine-check error and provides extended recovery capability.
The machine-check architecture provides several banks of reporting registers for recording
machine-check errors. Each bank of registers is associated with a specific hardware unit in the
processor. The primary focus of the machine checks is on bus and interconnect operations;
however, checks are also made of translation lookaside buffer (TLB) and cache operations.
machine-check errors. Each bank of registers is associated with a specific hardware unit in the
processor. The primary focus of the machine checks is on bus and interconnect operations;
however, checks are also made of translation lookaside buffer (TLB) and cache operations.
The machine-check architecture can correct some errors automatically and allow for reliable
restart of instruction execution. It also collects sufficient information for software to use in
correcting other machine errors not corrected by hardware.
restart of instruction execution. It also collects sufficient information for software to use in
correcting other machine errors not corrected by hardware.
See Chapter 14, “Machine-Check Architecture,” for more information on the machine-check
exception and the machine-check architecture.
exception and the machine-check architecture.