Intel architecture ia-32 User Manual
Vol. 3A 17-41
IA-32 ARCHITECTURE COMPATIBILITY
17.36.5 Performance-Monitoring Counters
The P6 family and Pentium processors provide two performance-monitoring counters for use in
monitoring internal hardware operations. These counters are event counters that can be
programmed to count a variety of different types of events, such as the number of instructions
decoded, number of interrupts received, or number of cache loads. Appendix A, “Performance-
Monitoring Events,” lists all the events that can be counted (Table A-12 for the P6 family
processors and Table A-13 for the Pentium processors). The counters are set up, started, and
stopped using two MSRs and the RDMSR and WRMSR instructions. For the P6 family proces-
sors, the current count for a particular counter can be read using the new RDPMC instruction.
monitoring internal hardware operations. These counters are event counters that can be
programmed to count a variety of different types of events, such as the number of instructions
decoded, number of interrupts received, or number of cache loads. Appendix A, “Performance-
Monitoring Events,” lists all the events that can be counted (Table A-12 for the P6 family
processors and Table A-13 for the Pentium processors). The counters are set up, started, and
stopped using two MSRs and the RDMSR and WRMSR instructions. For the P6 family proces-
sors, the current count for a particular counter can be read using the new RDPMC instruction.
The performance-monitoring counters are useful for debugging programs, optimizing code,
diagnosing system failures, or refining hardware designs. See Chapter 18, “Debugging and
Performance Monitoring,” for more information on these counters.
diagnosing system failures, or refining hardware designs. See Chapter 18, “Debugging and
Performance Monitoring,” for more information on these counters.
17.37. TWO WAYS TO RUN INTEL 286 PROCESSOR TASKS
When porting 16-bit programs to run on 32-bit IA-32 processors, there are two approaches
to consider:
to consider:
•
Porting an entire 16-bit software system to a 32-bit processor, complete with the old
operating system, loader, and system builder. Here, all tasks will have 16-bit TSSs. The
32-bit processor is being used as if it were a faster version of the 16-bit processor.
operating system, loader, and system builder. Here, all tasks will have 16-bit TSSs. The
32-bit processor is being used as if it were a faster version of the 16-bit processor.
•
Porting selected 16-bit applications to run in a 32-bit processor environment with a 32-bit
operating system, loader, and system builder. Here, the TSSs used to represent 286 tasks
should be changed to 32-bit TSSs. It is possible to mix 16 and 32-bit TSSs, but the benefits
are small and the problems are great. All tasks in a 32-bit software system should have
32-bit TSSs. It is not necessary to change the 16-bit object modules themselves; TSSs are
usually constructed by the operating system, by the loader, or by the system builder. See
Chapter 16, “Mixing 16-Bit and 32-Bit Code,” for more detailed information about mixing
16-bit and 32-bit code.
operating system, loader, and system builder. Here, the TSSs used to represent 286 tasks
should be changed to 32-bit TSSs. It is possible to mix 16 and 32-bit TSSs, but the benefits
are small and the problems are great. All tasks in a 32-bit software system should have
32-bit TSSs. It is not necessary to change the 16-bit object modules themselves; TSSs are
usually constructed by the operating system, by the loader, or by the system builder. See
Chapter 16, “Mixing 16-Bit and 32-Bit Code,” for more detailed information about mixing
16-bit and 32-bit code.
Because the 32-bit processors use the contents of the reserved word of 16-bit segment descrip-
tors, 16-bit programs that place values in this word may not run correctly on the 32-bit
processors.
tors, 16-bit programs that place values in this word may not run correctly on the 32-bit
processors.