NEC uPD78052(A) User Manual
103
CHAPTER 5 CPU ARCHITECTURE
Figure 5-11. Data Memory Addressing (
µ
PD78054, 78054Y)
0000H
General Registers
32
×
8 bits
Internal ROM
32768
×
8 bits
Internal Buffer RAM
32
×
8 bits
External Memory
31360
×
8 bits
Reserved
8000H
7FFFH
7FFFH
FA80H
FA7FH
FA7FH
FAC0H
FABFH
FABFH
FAE0H
FADFH
FADFH
FEE0H
FEDFH
FEDFH
FF00H
FEFFH
FEFFH
FFFFH
Internal High-speed RAM
1024
×
8 bits
Reserved
FB00H
FAFFH
FAFFH
FF20H
FF1FH
FF1FH
FE20H
FE1FH
FE1FH
Special Function
Registers (SFRs)
Registers (SFRs)
256
×
8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Addressing
Direct Addressing
Register Indirect
Addressing
Addressing
Based Addressing
Based Indexed
Addressing
Addressing