Intel Pentium M 730 RH80536GE0252M User Manual

24

  

 

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1. Unless otherwise noted, all specifications in this table are based on latest post-silicon measurements 

available at the time of publication.

2. These voltages are targets only. A variable voltage source should exist on systems in the event that a 

different voltage is required. See 

 for more information. The VID bits will set the typical 

V

CC

 with the minimum being defined according to current consumption at that voltage.

3. The voltage specification requirements are measured at the system board socket ball with a 100 MHz 

bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M

Ω

 minimum impedance. The maximum 

length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not 
coupled in the scope probe.

4. Refer to 

 to 

 and 

 to 

 for the minimum, typical, and maximum V

CC

 (measured 

at the system board socket ball) allowed for a given current. The processor should not be subjected to any 
V

CC

 and I

CC

 combination wherein V

CC

 exceeds V

CC_MAX

 for a given current. Failure to adhere to this 

specification can affect the long term reliability of the processor.

5. V

CC_MIN

 is defined at I

CC_MAX

. 

6. The current specified is also for AutoHALT State.
7. Typical V

CC

 indicates the VID encoded voltage. Voltage supplied must conform to the load line specification 

shown in 

.

8. The maximum instantaneous current the processor will draw while the thermal control circuit is active as 

indicated by the assertion of PROCHOT# is the same as the maximum I

CC

 for the processor.

9. Maximum specifications for I

CC

 Core, I

CC

 Stop-Grant, I

CC

 Sleep, and I

CC

 Deep Sleep are specified at V

CC

 

Static Max. derived from the tolerances in 

J

 Max., and under maximum signal 

loading conditions.

V

CC

 

V

CC

 for core logic

 

   Maximum Performance Mode

 

    Battery Optimized Mode

1.3
1.2

V

2, 3, 4, 
5, 7, 8,11

VCCVID

VID supply voltage

-5%

1.2

+10%

V

2, 12

V

CCDPRSLP

 

Transient Deeper Sleep voltage

0.91

1.00

1.09

V

2

V

CCDPRSLP,DC

 

Static Deeper Sleep voltage

0.95

1.00

1.05

V

2

I

CC

Current for V

CC

 at core frequency

   2.60 GHz & 1.3 V

 

   2.50 GHz & 1.3 V

 

   2.40 GHz & 1.3 V

 

   2.20 GHz & 1.3 V

 

   2.00 GHz & 1.3 V

 

   1.90 GHz & 1.3 V

 

   1.80 GHz & 1.3 V

 

   1.70 GHz & 1.3 V

 

   1.60 GHz & 1.3 V

 

   1.50 GHz & 1.3 V

 

   1.40 GHz & 1.3 V

 

    1.20 GHz  &  1.2 V

38.8
37.7
36.7
34.5
33.3
32.2
31.0
29.9
28.7
27.5
26.3
22.1

A

4, 5, 8, 9

I

VCCVID

Current for VID supply

300

mA

I

SG

NT

, I

SLP

I

CC 

Stop-Grant and I

CC

Sleep at

 

    1.3 V (for > 2.0 GHz)

 

    1.3 V (for <= 2.0 GHz)

 

     1.2 V

10.5
10.1

8.9

A

6, 9

I

DSLP

I

CC

 Deep Sleep at

    1.3 V

 

     1.2 V

9.0
8.3

A

9

I

DPRSLP

I

CC

 Deeper Sleep at 1.0V

6.9

A

I

TCC

I

CC 

TCC active

I

CC

A

8

I

CC PLL

I

CC

 for PLL pins

60

mA

10