Intel Pentium M 730 RH80536GE0252M User Manual
Product codes
RH80536GE0252M
Electrical Specifications
22
Mobile Intel
Pentium
4 Processor-M Datasheet
2.7
Asynchronous GTL+ Signals
Mobile Intel Pentium 4 Processor-M does not utilize CMOS voltage levels on any signals that
connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers. Legacy output
FERR#/PBE# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) use GTL+ output
buffers. All of these signals follow the same DC requirements as AGTL+ signals, however the
outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major
difference between GTL+ and AGTL+). These signals do not have setup or hold time specifications
in relation to BCLK[1:0]. However, all of the Asynchronous GTL+ signals are required to be
asserted for at least two BCLKs in order for the processor to recognize them. See
connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers. Legacy output
FERR#/PBE# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) use GTL+ output
buffers. All of these signals follow the same DC requirements as AGTL+ signals, however the
outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major
difference between GTL+ and AGTL+). These signals do not have setup or hold time specifications
in relation to BCLK[1:0]. However, all of the Asynchronous GTL+ signals are required to be
asserted for at least two BCLKs in order for the processor to recognize them. See
and
for the DC and AC specifications for the Asynchronous GTL+ signal groups.
2.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the Mobile Intel Pentium 4 Processor-M be first in the TAP chain and followed
by any other components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of the
appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#. Two
copies of each signal may be required, with each driving a different voltage level.
recommended that the Mobile Intel Pentium 4 Processor-M be first in the TAP chain and followed
by any other components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of the
appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#. Two
copies of each signal may be required, with each driving a different voltage level.
2.9
System Bus Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] are output signals used to select the frequency of the processor input clock
(BCLK[1:0]).
(BCLK[1:0]).
associated with each combination. The required frequency is determined by the processor, chipset,
and clock synthesizer. All agents must operate at the same frequency.
and clock synthesizer. All agents must operate at the same frequency.
The Mobile Intel Pentium 4 Processor-M currently operates at a 400-MHz system bus frequency
(selected by a 100-MHz BCLK[1:0] frequency). Individual processors will only operate at their
specified system bus frequency.
(selected by a 100-MHz BCLK[1:0] frequency). Individual processors will only operate at their
specified system bus frequency.
For more information about these pins refer to
guidelines.
Table 5. BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1
BSEL0
Function
L
L
100 MHz
L
H
RESERVED
H
L
RESERVED
H
H
RESERVED