Intel Pentium M 730 RH80536GE0252M User Manual
Product codes
RH80536GE0252M
Electrical Specifications
34
Mobile Intel
Pentium
4 Processor-M Datasheet
Figure 7. ITPCLKOUT[1:0] Output Buffer Diagram
NOTES:
1. See
for range of Ron.
2. The Vcc referred to in this figure is the instantaneous Vcc.
3. Refer to the appropriate platform design guidelines for the value of Rext.
3. Refer to the appropriate platform design guidelines for the value of Rext.
Table 17. BSEL [1:0] and VID[4:0] DC Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50 V.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50 V.
2.12
AGTL+ System Bus Specifications
Routing topology recommendations may be found in the Mobile Intel
Pentium
4 Processor-M
and Intel
845MP/845MZ Chipset Platform Design Guide. Termination resistors are not required
for most AGTL+ signals, as these are integrated into the processor silicon.
Valid high and low levels are determined by the input buffers which compare a signal’s voltage
with a reference voltage called GTLREF (known as V
with a reference voltage called GTLREF (known as V
REF
in previous documentation).
lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be
generated on the system board using high precision voltage divider circuits. It is important that the
system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance
system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance
Vcc
Ron
Processor Package
Rext
To Debug Port
Symbol
Parameter
Min
Max
Unit
Notes
1
Ron
(BSEL)
Buffer On Resistance
9.2
14.3
Ω
2
Ron
(VID)
Buffer On Resistance
7.8
12.8
Ω
2
I
HI
Pin Leakage Hi
N/A
100
µA
3