Intel Pentium M 730 RH80536GE0252M User Manual

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1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All 

Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge 
at 0.5*V

CC

3. These signals may be driven asynchronously.
4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the 

assertion and before the deassertion of PROCHOT# for the processor to complete current instruction 
execution. This specification refers to PROCHOT# when asserted by the processor. There are no pulse width 
requirements for when PROCHOT# is asserted by the system.

6. See 

Section 7.2 

for additional timing requirements for entering and leaving the low power states.

NOTES: 

1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.

T35: Asynch GTL+ Input Pulse Width

2

BCLKs

T36: PWRGOOD to RESET# de-assertion 

time

1

10

ms

T37: PWRGOOD Inactive Pulse Width

10

BCLKs

4

T38: PROCHOT# pulse width

500

us

5

T39: THERMTRIP# to Vcc Removal

0.5

s

T40: FERR# Valid Delay from STPCLK# 

deassertion

0

5

BCLKs

T45:  Reset Configuration Signals (A[31:3]#, 

BR0#, INIT#, SMI#) Setup Time

4

BCLKs

1

T46: Reset Configuration Signals (A[31:3]#, 

BR0#, INIT#, SMI#) Hold Time

2

20

BCLKs

2