Intel Pentium M 730 RH80536GE0252M User Manual

40

  

 

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1. Input signals other than RESET# must be held constant in the Sleep state.
2. The BCLK can be stopped after DPSLP# is asserted. The BCLK must be turned on and within specification 

before DPSLP# is deasserted.

.

The following figures are used in conjunction with the AC timing tables, 

 through 

 For 

 through 

, the following apply:

1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V

CROSS

) of the 

BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the 
processor core.

2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or 

data) at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data 
strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated 
address strobe. All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor 
core silicon.

3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V

CROSS

. All AGTL+ strobe signal 

timings are referenced at GTLREF at the processor core silicon.

4. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*V

CC

 at the processor pins. All TAP 

signal timings (TMS, TDI, etc.) are referenced at 0.5*V

CC

 at the processor pins.

The circuit used to test the AC specifications is shown in 

T70: SLP# Signal Hold Time from Stop Grant 
Cycle Completion

100

BCLKs

T71: Input Signals Stable to SLP# Assertion

10

BCLKs

1

T72: SLP# to DPSLP# Assertion

10

BCLKs

T73: Deep Sleep PLL Lock Latency

0

30

µ

s

2

T74: SLP# Hold Time from PLL Lock

0

ns

T75: STPCLK# Hold Time from SLP# 
Deassertion

10

BCLKs

T76: Input Signal Hold Time from SLP# 
Deassertion

10

BCLKs

T77: VID[4:0] Output Valid Delay from DPSLP# 

 

Assertion

0

10

µ

s