Intel Pentium M 730 RH80536GE0252M User Manual





 4 Processor-M Datasheet  

51

Source synchronous data transfer requires the clean reception of data signals and their associated 
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage 
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be 
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive 
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity and can 
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and 
undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI) 
effects. For these reasons, it is important that the designer work to achieve a solution that provides 
acceptable signal quality across all systematic variations encountered in volume manufacturing.

This section documents signal quality metrics used to derive topology and routing guidelines 
through simulation and for interpreting results for signal quality measurements of actual designs.

 describes the signal quality specifications at the processor pads for the processor system 

bus clock (BCLK) signals. 

 describes the signal quality waveform for the system bus 

clock at the processor pads. 

1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M 

frequencies.

2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute 

voltage the BCLK signal can dip back to after passing the V

IH

 (rising) or V

IL

 

(falling) voltage limits. This 

specification is an absolute value.

BCLK[1:0] Overshoot

N/A

0.30

V

BCLK[1:0] Undershoot

N/A

0.30

V

BCLK[1:0] Ringback Margin

0.20

N/A

V

2

BCLK[1:0] Threshold Region

N/A

0.10

V