Cypress Semiconductor 3033 User Manual
Document Number: 002-18414 Rev. **
Page 14 of 33
PRELIMINARY
CYBT-013033-01
Microprocessor Unit
Overview
The CYBT-013033-01 microprocessor unit runs software from the Link Control (LC) layer up to the stack and Application layer. In the
HCI mode of operation the stack will be run on the external host. The microprocessor is based on the Cortex-M3 32-bit RISC processor
with embedded ICE-RT debug and JTAG interface units. The microprocessor also includes 848 KB of ROM memory for program
storage and boot ROM, 352 KB of RAM for data scratch-pad, and patch RAM code.
HCI mode of operation the stack will be run on the external host. The microprocessor is based on the Cortex-M3 32-bit RISC processor
with embedded ICE-RT debug and JTAG interface units. The microprocessor also includes 848 KB of ROM memory for program
storage and boot ROM, 352 KB of RAM for data scratch-pad, and patch RAM code.
The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations,
including automatic host transport selection from UART transport without external NVRAM. At power-up, the lower layer protocol stack
is executed from the internal ROM.
including automatic host transport selection from UART transport without external NVRAM. At power-up, the lower layer protocol stack
is executed from the internal ROM.
External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches
can be downloaded from the host to the device through the UART transport.
can be downloaded from the host to the device through the UART transport.
One-Time Programmable Memory
The CYBT-013033-01 includes a One-Time Programmable (OTP) memory, allowing manufacturing customization and avoiding the
need for an on-board NVRAM. If customization is not required, then the OTP does not need to be programmed. Whether the OTP is
programmed or not, it is disabled after the boot process completes to save power.
need for an on-board NVRAM. If customization is not required, then the OTP does not need to be programmed. Whether the OTP is
programmed or not, it is disabled after the boot process completes to save power.
The OTP size is 2048 bytes.
The OTP is designed to store a minimal amount of information. Aside from OTP data, most user configuration information will be
downloaded into RAM after the CYBT-013033-01 boots up and is ready for host transport communication. The OTP contents are
limited to:
downloaded into RAM after the CYBT-013033-01 boots up and is ready for host transport communication. The OTP contents are
limited to:
■
Parameters required prior to downloading user configuration to RAM.
■
Parameters unique to each part and each customer (i.e., the BD_ADDR, and software license key).
The following are typical parameters programmed into the OTP memory:
■
BD_ADDR
■
Software license key
■
Output power calibration
■
Frequency trimming
■
Initial status LED drive configuration
The OTP contents also include a static error correction table to improve yield during the programming process as well as forward error
correction codes to eliminate any long-term reliability problems. The OTP contents associated with error correction are not visible by
customers.
correction codes to eliminate any long-term reliability problems. The OTP contents associated with error correction are not visible by
customers.
Peripheral Transport Unit
This section discusses the UART peripheral interface. The CYBT-013033-01 has a 1040-byte transmit and receive FIFO, which is
large enough to hold the entire payload of the largest EDR Bluetooth packet (3-DH5).
large enough to hold the entire payload of the largest EDR Bluetooth packet (3-DH5).
HCI Transport Detection Configuration
Note: HCI transport detection is only valid for the HCI operating mode.
The CYBT-013033-01 supports the following interface types for the HCI transport from the host:
■
UART (H4)
Only one host interface can be active at a time. The firmware performs a transport detect function at boot-time to determine which
host is the active transport. It can auto-detect UART interfaces, but the SPI interface must be selected by strapping the SCL pin to 0.
host is the active transport. It can auto-detect UART interfaces, but the SPI interface must be selected by strapping the SCL pin to 0.
■
The complete algorithm is summarized as follows:
■
Determine if any local NVRAM contains a valid configuration file. If it does and a transport configuration entry is present, select the
active transport according to entry, and then exit the transport detection routine.
active transport according to entry, and then exit the transport detection routine.
■
Look for CTS_N = 0 on the UART interface. If it is present, select UART.
■
Repeat Step 2 and Step 3 until transport is determined.