IBM Intel Xeon E5606 49Y3776 User Manual

114

VCCPWRGOOD

I

VCCPWRGOOD (Power Good) is a processor input. The processor requires this 

signal to be a clean indication that BCLK, V

CC

, V

CCPLL

, V

TTA

 and V

TTD

 supplies 

are stable and within their specifications. 'Clean' implies that the signal will 

remain low (capable of sinking leakage current), without glitches, from the 

time that the power supplies are turned on until they come within specification. 

The signal must then transition monotonically to a high state. VCCPWRGOOD 

can be driven inactive at any time, but BCLK and power must again be stable 

before a subsequent rising edge of VCCPWRGOOD. In addition at the time 

VCCPWRGOOD is asserted RESET# must be active. The VCCPWRGOOD signal 

must be supplied to the processor; it is used to protect internal circuits against 

voltage sequencing issues. It should be driven high throughout boundary scan 

operation.

V

CCPLL

I

Analog Power for Clocks.

V

DDQ

I

Power supply for the DDR3 interface.

VTT_VID[4:2]

O

VTT_VID[4:2] is used to support automatic selection of power supply voltages 

(V

TT

). The voltage supply for this signal must be valid before the VR can supply 

V

TT

 to the processor. Conversely, the VR output must be disabled until the 

voltage supply for the VID signal become valid. The VID signal is needed to 

support the processor voltage specification variations. The VR must supply the 

voltage that is requested by the signal.

V

TTA

I

Power for the analog portion of the Intel QuickPath and Shared Cache.

V

TTD

I

Power for the digital portion of the Intel QuickPath and Shared Cache.

VDDPWRGOOD

I

VDDPWRGOOD is an input that indicates the VDDQ power supply is good. The 

processor requires this signal to be a clean indication that the Vddq power 

supply is stable and within their specifications.  "Clean" implies that the signal 

will remain low (capable of sinking leakage current), without glitches, from the 

time that the VDDQ supply is turned on until it comes within specification. The 

signals must then transition monotonically to a high state. 
The VDDPWRGOOD signal must be supplied to the processor. This signal is 

used to protect internal circuits against voltage sequencing issues.

VID[7:0]

I/O

VID[7:0] (Voltage ID) are output signals that are used to support automatic 

selection of power supply voltages (V

CC

). The voltage supply for these signals 

must be valid before the VR can supply V

CC

 to the processor. Conversely, the 

VR output must be disabled until the voltage supply for the VID signals become 

valid. The VID signals are needed to support the processor voltage specification 

variations. The VR must supply the voltage that is requested by the signals, or 

disable itself.
MSID[2:0] - Market Segment ID, or MSID are provided to indicate the Market 

Segment for the processor and may be used for future processor compatibility 

or for keying. In addition, MSID protects the platform by preventing a higher 

power processor from booting in a platform designed for lower power 

processors. This value is latched from the platform in to the CPU, on the rising 

edge of VTTPWRGOOD, during the cold boot power up sequence.
CSC[2:0] - Current Sense Configuration bits are output signals for ISENSE gain 

setting.This value is latched on the rising edge of VTTPWRGOOD.

2

V

TTD_SENSE

V

SS_SENSE_VTT

O
O

V

TTD_SENSE

 and V

SS_SENSE_VTT

 provide an isolated, low impedance connection 

to the processor core power and ground. They can used to sense or measure 

power near the silicon.

VTTPWRGOOD

I

The processor requires this input signal to be a clean indication that the VTT 

power supply is stable and within their specifications. 'Clean' implies that the 

signal will remain low (capable of sinking leakage current), without glitches, 

from the time that the power supplies are turned on until they come within 

specification. The signal must then transition monotonically to a high state. to 

determine that the VTT voltage is stable and within specification. Note it is not 

valid for VTTPWRGOOD to be deasserted while VCCPWRGOOD is asserted.

1. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.

2. VID[7:0] is an Input only during Power On Configuration. It is an Output signal during normal operation.