IBM Intel Xeon E5620 49Y3773 User Manual
Product codes
49Y3773
Features
166
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the C1 state. See the Intel® 64 and IA-32 Architecture Software Developer's
Manuals, Volume III: System Programmer's Guide for more information.
state or the C1 state. See the Intel® 64 and IA-32 Architecture Software Developer's
Manuals, Volume III: System Programmer's Guide for more information.
While in C1/C1E state, the processor will process bus snoops and snoops from the
other threads.
other threads.
To operate within specification, BIOS must enable the C1E feature for all installed
processors.
processors.
8.2.1.3
C3 State
Individual threads of the processor can enter the C3 state by initiating a P_LVL2 I/O
read to the P_BLK or an MWAIT(C3) instruction. Before entering core C3, that core
flushes the contents of its caches. Caches shared among cores are not impacted.
Except for the caches, the processor core maintains all its architectural state while in
the C3 state. All of the clocks in the processor core are stopped in the C3 state.
read to the P_BLK or an MWAIT(C3) instruction. Before entering core C3, that core
flushes the contents of its caches. Caches shared among cores are not impacted.
Except for the caches, the processor core maintains all its architectural state while in
the C3 state. All of the clocks in the processor core are stopped in the C3 state.
Because the core’s caches are flushed, the processor keeps the core in the C3 state
when the processor detects a snoop on the Intel QuickPath Interconnect Link or when
another logical processor in the same package accesses cacheable memory. The
processor core will transition to the C0 state upon occurrence of an interrupt. RESET#
will cause the processor core to initialize itself.
when the processor detects a snoop on the Intel QuickPath Interconnect Link or when
another logical processor in the same package accesses cacheable memory. The
processor core will transition to the C0 state upon occurrence of an interrupt. RESET#
will cause the processor core to initialize itself.
8.2.1.4
C6 State
Individual threads of the processor can enter the C6 state by initiating a P_LVL3 read to
the P_BLK or an MWAIT(C6) instruction. Before entering core C6, that core flushes the
contents of its caches. Caches shared among cores are not impacted. The processor
achieves additional power savings in the core C6 state.
the P_BLK or an MWAIT(C6) instruction. Before entering core C6, that core flushes the
contents of its caches. Caches shared among cores are not impacted. The processor
achieves additional power savings in the core C6 state.
8.2.2
Package Power State Descriptions
The package supports C0, C1/C1E, C3 and C6 power states. The package power state
is automatically resolved by the processor depending on the core power states and
permission from the rest of the system as described below.
is automatically resolved by the processor depending on the core power states and
permission from the rest of the system as described below.
8.2.2.1
Package C0 State
This is the normal operating state for the processor. The processor remains in the
Normal state when at least one of its cores is in the C0 or C1 state or when another
component in the system has not granted permission to the processor to go into a low
power state. Individual components of the processor may be in low power states while
the package in C0.
Normal state when at least one of its cores is in the C0 or C1 state or when another
component in the system has not granted permission to the processor to go into a low
power state. Individual components of the processor may be in low power states while
the package in C0.
8.2.2.2
Package C1/C1E State
The package will enter the C1/C1E low power state when at least one core is in the
C1/C1E state and the rest of the cores are in a C1/C1E or deeper power state. The
processor will also enter the C1/C1E state when all cores are in a power state lower
than C1/C1E but the package low power state is limited to C1/C1E via the
PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically
transition to the lowest power operating point (lowest supported voltage and associated
frequency). When entering the C1E state, the processor will first switch to the lowest
bus ratio and then transition to the lower VID. No notification to the system occurs
upon entry to C1/C1E.
C1/C1E state and the rest of the cores are in a C1/C1E or deeper power state. The
processor will also enter the C1/C1E state when all cores are in a power state lower
than C1/C1E but the package low power state is limited to C1/C1E via the
PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically
transition to the lowest power operating point (lowest supported voltage and associated
frequency). When entering the C1E state, the processor will first switch to the lowest
bus ratio and then transition to the lower VID. No notification to the system occurs
upon entry to C1/C1E.