IBM Intel Xeon E5620 49Y3773 User Manual
Product codes
49Y3773
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
167
Features
8.2.2.3
Package C3 State
The package will enter the C3 low power state when all cores are in the C3 or lower
power state and the processor has been granted permission by the other component(s)
in the system to enter the C3 state. The package will also enter the C3 state when all
cores are in an idle state lower than C3 but other component(s) in the system have
only granted permission to enter C3.
power state and the processor has been granted permission by the other component(s)
in the system to enter the C3 state. The package will also enter the C3 state when all
cores are in an idle state lower than C3 but other component(s) in the system have
only granted permission to enter C3.
If Intel QuickPath Interconnect L1 has been granted, the processor will disable some
clocks and PLLs and for processors with an integrated memory controller, the DRAM will
be put into self-refresh.
clocks and PLLs and for processors with an integrated memory controller, the DRAM will
be put into self-refresh.
8.2.2.4
Package C6 State
The package will enter the C6 low power state when all cores are in the C6 or lower
power state and the processor has been granted permission by the other component(s)
in the system to enter the C6 state. The package will also enter the C6 state when all
cores are in an idle state lower than C6 but the other component(s) have only granted
permission to enter C6.
power state and the processor has been granted permission by the other component(s)
in the system to enter the C6 state. The package will also enter the C6 state when all
cores are in an idle state lower than C6 but the other component(s) have only granted
permission to enter C6.
If Intel QuickPath Interconnect L1 has been granted, the processor will disable some
clocks and PLLs. The shared cache will enter a deep sleep state. Additionally, for
processors with an integrated memory controller, the DRAM will be put into self-refresh.
clocks and PLLs. The shared cache will enter a deep sleep state. Additionally, for
processors with an integrated memory controller, the DRAM will be put into self-refresh.
8.2.3
Intel Xeon Processor 5600 Series C-State Power
Specifications
lists C-state power specifications for various processor SKU’s.
Notes:
1.
Specifications are at T
CASE
= 50 C with all cores in the specified C-state.
2.
Standard/Basic SKUs.
8.3
Sleep States
The processor supports the ACPI sleep states S0, S1, S3, and S4/S5 as shown in
. For information on ACPI S-states and related terminology, refer to the
Advanced Configuration and Power Interface Specification. The S-state transitions are
coordinated by the processor in response PM Request (PMReq) messages from the
chipset. The processor itself will never request a particular S-state.
coordinated by the processor in response PM Request (PMReq) messages from the
chipset. The processor itself will never request a particular S-state.
Table 8-3.
Processor C-State Power Specifications
Package
C-State
1
Intel® Xeon® Processor 5600 Series
TDP=130 W
TDP=95W
TDP=80W
2
TDP=60W
TDP=40W
C1E
37 W
32 W
37/40 W
25 W
22 W
C3
32 W
28 W
33/33 W
20 W
18 W
C6
12 W
10 W
12/14 W
8 W
8 W