Intel E7-2803 AT80615006438AB User Manual
Product codes
AT80615006438AB
Datasheet Volume 2 of 2
31
Memory Controller (Mbox)
7
Memory Controller (Mbox)
The Intel Xeon Processor E7-8800/4800/2800 Product Families consists of two
integrated memory controllers. The memory controller (Mbox) contains the interface
logic to Intel 7500 Scalable Memory Buffer via Intel SMI interface (formerly “Fully
Buffered DIMM 2 interface”). Mbox issues memory read and write commands per Intel
SMI protocol and schedules them with respect to DDR III timing. The other main
function of the memory controller (Mbox) is the generating and checking of advanced
ECC.
integrated memory controllers. The memory controller (Mbox) contains the interface
logic to Intel 7500 Scalable Memory Buffer via Intel SMI interface (formerly “Fully
Buffered DIMM 2 interface”). Mbox issues memory read and write commands per Intel
SMI protocol and schedules them with respect to DDR III timing. The other main
function of the memory controller (Mbox) is the generating and checking of advanced
ECC.
Each memory controller (Mbox) supports two Intel SMI channels, for a total of 4 Intel
SMI channels per socket. One Mbox supports a pair of channels operating in lock-step.
This minimizes latency and more importantly enables x8 DDDC. Minimum transfer
burst of four ticks in DDR3 support for burst length 4 mode (BL4).
SMI channels per socket. One Mbox supports a pair of channels operating in lock-step.
This minimizes latency and more importantly enables x8 DDDC. Minimum transfer
burst of four ticks in DDR3 support for burst length 4 mode (BL4).
7.1
New Features on Intel Xeon Processor E7-8800/
4800/2800 Product Families
• 32 GB DIMM support
• Intel
• Intel
®
x4 Double Device Data Correction (DDDC)
7.2
Memory Controller (Mbox) Support
• DDR3 protocol, with operating DDR frequency of 800-1067
• 4 ticks burst mode (8 ticks burst mode not supported)
• 1 GB to 32 GB DIMM
• 1-Gb, 2-Gb, and 4 Gb (x4 and x8) devices
• Single, dual and Quad-rank DIMM support
• Minimum size of 2 GB per Mbox (2 channels, 1 DIMM per channel, 1 Gb x8 devices,
• 4 ticks burst mode (8 ticks burst mode not supported)
• 1 GB to 32 GB DIMM
• 1-Gb, 2-Gb, and 4 Gb (x4 and x8) devices
• Single, dual and Quad-rank DIMM support
• Minimum size of 2 GB per Mbox (2 channels, 1 DIMM per channel, 1 Gb x8 devices,
single rank DIMMs=1 GB DIMMs)
• Support for four and eight banks
• Supports two Intel SMI channel channels operating in lockstep. Each Intel SMI
• Supports two Intel SMI channel channels operating in lockstep. Each Intel SMI
channel is connected to a Intel 7500 Scalable Memory Buffer (Intel SMI-DDR3
bridge).
bridge).
• A maximum of 32 ranks per locked-step pair of Intel SMI links. (16 ranks per Intel
SMI channel).
• Mixing of DIMM types is allowed (with a maximum of four types per channel) as
long as each of the two lock-stepped channels are populated identically.
— No variable latency access within an Intel SMI channel is supported. The
latency of all DIMMs is equalized to the latency of the last DIMM.
• Maximum eight DIMMs per memory controller. (Four DIMMS per Intel 7500
Scalable Memory Buffer.)
• Double Device Data Correction (DDDC) is only supported for DIMMs with X4
devices. Single Device Data Correction (SDDC) is supported for both X4 and X8
devices. Also, all ranks will need to default to SDDC if there is a mix of X4 and X8
DIMMs behind a memory controller
devices. Also, all ranks will need to default to SDDC if there is a mix of X4 and X8
DIMMs behind a memory controller