Intel E7-2803 AT80615006438AB User Manual
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Product codes
AT80615006438AB
Introduction
8
Datasheet Volume 2 of 2
— Support for up to 16 DDR3 DIMMs per socket. Four DIMMs per Intel 7500
Scalable Memory Buffer
— Support for DDR III 800, 978, 1067 MHz memory speeds
— Support for 1, 2 and 4 Gigabit DRAM technology
— Support for up to 32 GB Quad Rank DIMM
— Support low voltage LV-RDIMMs (also called DDR3L)
— Support for 1.5 V/1.35 V High Density Reduced Load RDIMMs (also called
— Support for 1, 2 and 4 Gigabit DRAM technology
— Support for up to 32 GB Quad Rank DIMM
— Support low voltage LV-RDIMMs (also called DDR3L)
— Support for 1.5 V/1.35 V High Density Reduced Load RDIMMs (also called
LRDIMM, which is Load Reduced DIMM)
• Memory RAS features including:
— Support for X4 Double chip fail
— Memory ECC support including correction of x4 and x8 chip-fail
— Failover mode to operate with a single lane failure per channel per direction
— Support for memory mirroring and resilvering, Demand and Patrol Scrubbing
— Support for memory migration
— Memory ECC support including correction of x4 and x8 chip-fail
— Failover mode to operate with a single lane failure per channel per direction
— Support for memory mirroring and resilvering, Demand and Patrol Scrubbing
— Support for memory migration
• Intel QuickPath Interconnect RAS features including:
— Self-healing via link width reduction
— Link-level retry mechanism provides hardware retry on link transmission errors
— 8-bit CRC or 16-bit rolling CRC
— Error reporting mechanisms including Data Poisoning indication and Viral bit
— Support for lane reversal as well as polarity reversal at the Intel QuickPath
— Link-level retry mechanism provides hardware retry on link transmission errors
— 8-bit CRC or 16-bit rolling CRC
— Error reporting mechanisms including Data Poisoning indication and Viral bit
— Support for lane reversal as well as polarity reversal at the Intel QuickPath
Interconnect links
— Support for Platform-level RAS features: Hot Add/Remove, dynamic
reconfiguration
— High-bandwidth ECC protected Crossbar Router with route-through capability
• Platform security capabilities using Intel
®
Trusted Execution Technology
(Intel
®
TXT)
• Intel
®
AES New Instructions (Intel
®
AES-NI)
• Power management technology to best manage power across ten cores, including
support for Enhanced Intel SpeedStep
®
Technology, Intel
®
Thermal Monitor, and
Intel Thermal Monitor 2
— Dynamic monitoring of die temperature via digital thermal sensors
• Sideband read/write access to un-core logic via PECI and JTAG
• Support for sideband read access through PECI to core error log MSRs
• System management mode (SMM)
• Supports an SMBus Specification, Revision 2.0 slave interface for server
• Support for sideband read access through PECI to core error log MSRs
• System management mode (SMM)
• Supports an SMBus Specification, Revision 2.0 slave interface for server
management components, that is, PIROM
• Manageability Components including an EEPROM/Processor Information ROM
accessed through SMBus interface
• Machine Check Architecture
• Support for Intel
• Support for Intel
®
Virtualization Technology (Intel
®
VT) for IA-32 Intel
®
Architecture 2 (Intel
®
VT-x 2)
— Allows a platform to run multiple Operating systems and applications in
independent partitions or “containers”. One physical compute system can
function as multiple “virtual” systems.