Intel E7-2860 AT80615005781AB User Manual

26

Intel

®

 Xeon

®

 Processor E7-8800/4800/2800 Product Families

September 2012

Specification Update

Problem:

An unexpected page fault (#PF) or EPT violation may occur for a page under the 

following conditions:

• The paging structures initially specify no valid translation for the page.
• Software on one logical processor modifies the paging structures so that there is a 

valid translation for the page (e.g., by setting to 1 the present bit in one of the 
paging-structure entries used to translate the page).

• Software on another logical processor observes this modification (e.g., by accessing 

a linear address on the page or by reading the modified paging-structure entry and 
seeing value 1 for the present bit).

• Shortly thereafter, software on that other logical processor performs a store to a 

linear address on the page.

In this case, the store may cause a page fault or EPT violation that indicates that there 

is no translation for the page (e.g., with bit 0 clear in the page-fault error code, 

indicating that the fault was caused by a not-present page). Intel has not observed this 

erratum with any commercially available software.

Implication:

An unexpected page fault may be reported. There are no other side effects due to this 

erratum.

Workaround:

System software can be constructed to tolerate these unexpected page faults. See 

Section “Propagation of Paging-Structure Changes to Multiple Processors” of Volume 3A 

of the IA-32 Intel® Architecture Software Developer's Manual, for recommendations 

for software treatment of asynchronous paging-structure updates.

Status:

For the steppings affected, see the 

Problem:

On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is 

reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory 

access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due 

to this erratum, PS of such an entry is ignored and no page fault will occur due to its 

being set.

Implication:

Software may not operate properly if it relies on the processor to deliver page faults 

when reserved bits are set in paging-structure entries.

Workaround:

Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to “1”. 

Status:

For the steppings affected, see the 

Problem:

The IO_SMI bit in SMRAM’s location 7FA4H is set to “1” by the processor to indicate a 

System Management Interrupt (SMI) occurred as the result of executing an instruction 

that reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by:
•

A non-I/O instruction

•

An event where an I/O read sets the IO_SMI bit but another interrupt is taken 
before the recognition of the SMI event 

•

A REP INS instruction

•

An I/O read that redirects to MWAIT

Implication:

SMM handlers may get false IO_SMI indication.

Workaround:

The SMM handler has to evaluate the saved context to determine if the SMI was 

triggered by an instruction that read from an I/O port. The SMM handler must not