Intel E7-2860 AT80615005781AB User Manual

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Intel

®

 Xeon

®

 Processor E7-8800/4800/2800 Product Families

September 2012

Specification Update

Workaround:

None identified.

Status:

For the steppings affected, see the 

Problem:

Under certain complex micro-architectural conditions, closely spaced data accesses 

that are split across cacheline boundaries may lead to a processor hang.

Implication:

Due to this erratum, the processor may hang. This erratum has not been observed with 

any general purpose operating systems.

Workaround:

None identified.

Status:

For the steppings affected, see the 

Problem:

Under certain timing conditions involving multiple cores, a cacheable load may appear 

to be ordered before an earlier cacheable locked instruction that accesses a different 

location.

Implication:

Locked instructions and subsequent loads may not occur in the expected order when 

run on multiple cores. In some circumstances this could lead to unpredictable system 

behavior.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the 

Problem:

If the VMCS link pointer is valid in the VMCS, VM entry instructions should check that 

the 32 bits referenced by that pointer contains the processor’s VMCS revision identifier 

and fail if it does not. Due to this erratum, VMRESUME may omit this check and thus 

not cause VM entry to fail in some cases.

Implication:

The revision identifier of the linked VMCS may not be checked. Intel has not observed 

this erratum with any commercially available software.

Workaround:

None identified.

Status:

For the steppings affected, see the 

Problem:

APIC timer interrupts intended to awaken from core C3 may be lost under certain 

timing conditions.

Implication:

Due to this erratum, a lost timer interrupt may cause the system to hang.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the 

Problem:

In cases when a WBINVD instruction evicts a line containing an address or data parity 

error (MCACOD of 0x124, and MSCOD of 0x10), the address of this error should be 

logged in the MCi_ADDR register. Due to this erratum, the logged address may be 

incorrect, even though MCi_Status.ADDRV (bit 63) is set.

Implication:

The address reported in MCi_ADDR may not be correct for cases of a parity error found 

during WBINVD execution.

Workaround:

None identified.

Status:

For the steppings affected, see the