Intel E7-4807 AT80615006432AB User Manual
Product codes
AT80615006432AB
Datasheet Volume 2 of 2
35
Memory Controller (Mbox)
7.5.2.1
Pre-conditions
• Assumes Master/Slave with identical memory types, and density.
• Assumes existing configuration limitations applicable to full mirror mode of
• Assumes existing configuration limitations applicable to full mirror mode of
operation.
7.5.2.2
Sample Scenario
• System manufacturer with tight control on OS kernel will configure the server
platform in partial memory mirroring mode.
• System configuration (SAD entries) is such that the software kernels will be loaded
in physical Home Agent/memory. That hardware is configured to operate in mirror
mode.
mode.
• System manufacturer may choose to give option to end user to have the system
configured in mirror mode, partial memory mode, or non-mirror mode.
7.5.2.3
Flow
At cold boot, along with other system initialization, the intended paired Home Agent
master/slave is configured in mirror mode, and mirroring is enabled for that pair.
master/slave is configured in mirror mode, and mirroring is enabled for that pair.
• Only the Master Home Agent will automatically re-direct all transactions to Slave in
the event of uncorrected errors.
• Non master Home Agent that encounters Uncorrected error will follow non mirrored
flows.
7.6
Mirroring Mode Restrictions
The following mirroring restrictions apply with the listed Tracker Modes:
• Tracker Mode 7 : Only supports intra-socket mirroring
• Tracker Mode 6 : Does not support mirroring
• Tracker Mode 4 : Master and slave should have same rhnid[4:3]
• Tracker Mode 5 : Master and slave should have same rhnid[4]
• Tracker Mode 6 : Does not support mirroring
• Tracker Mode 4 : Master and slave should have same rhnid[4:3]
• Tracker Mode 5 : Master and slave should have same rhnid[4]
For details on supported Tracker Modes please refer
.
Note:
Tracker Mode 7 does not support Memory Migration.
7.7
Intel
®
Dynamic Power Technology (Intel
®
DPT)
The Intel
®
Dynamic Power Technology allows OS/VMMs to vacate a logical memory
power node and trigger power state transition for the same. Each of the contiguous
ranges of memory that can be power managed is specified as a memory power node in
the ACPI MPST table. A memory power node is a logical memory region describing a
collection of physical memory components (for example, Ranks, DIMMs, Channels) that
can be transitioned in and out of a memory power state at the same time. a memory
power node can also be a portion of a physical memory component. Example: each
rank in a QR DIMM can be individual memory power nodes. memory power nodes are
defined by the contiguous address ranges. Hence if there is are holes in the address
range produced by a physical memory component, multiple memory power nodes are
created. For the Intel Xeon processor 7500 series-based platform, the memory power
node is at a branch (controller, riser) level granularity. Power states supported by
memory components varies across platforms. Each power state can have unique
ranges of memory that can be power managed is specified as a memory power node in
the ACPI MPST table. A memory power node is a logical memory region describing a
collection of physical memory components (for example, Ranks, DIMMs, Channels) that
can be transitioned in and out of a memory power state at the same time. a memory
power node can also be a portion of a physical memory component. Example: each
rank in a QR DIMM can be individual memory power nodes. memory power nodes are
defined by the contiguous address ranges. Hence if there is are holes in the address
range produced by a physical memory component, multiple memory power nodes are
created. For the Intel Xeon processor 7500 series-based platform, the memory power
node is at a branch (controller, riser) level granularity. Power states supported by
memory components varies across platforms. Each power state can have unique