Compal Electronics Inc PICONODE User Manual
PicoNode Integration Specification
26
7.3 Host Interface SPI Bus State Machine
This section illustrates the sequence of messages that can take place on the Host interface SPI
bus. The design and implementation of the actual state machine on the Host software is up to
the Host software designer. This diagram is provided to demonstrate the message sequence
over the SPI Bus. Note the usage of the turn-around delay, which is required in between each
step of message exchange. This delay is required by the Node and is currently defined as having
a time of 200 µs.
bus. The design and implementation of the actual state machine on the Host software is up to
the Host software designer. This diagram is provided to demonstrate the message sequence
over the SPI Bus. Note the usage of the turn-around delay, which is required in between each
step of message exchange. This delay is required by the Node and is currently defined as having
a time of 200 µs.
ARBITRATION
NIL
VALIDATION
IDLE
MMSG_REQ
SMSG_REQ
MMSG_PAYLOAD
SMSG_PAYLOAD
A
A
B
B
Turn-around
Delay
A
Turn-around
Delay
Turn-around
Delay
Turn-around
Delay
Turn-around
Delay
B
BOOT
Exchange of Arbitration
Message
Exchange of
Validation Message
Any
Non-Validation
Exchange of MHDR Message
Exchange of SHDR Message
Exchange of MMSG
Message
Any
Other SPI Bus
Traffic
Any
Other SPI Bus
Traffic
Exchange of SMSG
Message
Host (Master) Has
Message to Send
SRQ Asserted by
Slave (Node)
Non-Arbitration
Response
Unexpected
SMSG_RSP
Figure 9 Host Interface SPI Bus State Machine