Compal Electronics Inc PICONODE User Manual
PicoNode Integration Specification
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7. The Host starts the SPI data transaction. This is accomplished by driving the Node CS line
low and then having the Host toggle the SCLK, and MOSI lines and having the Node toggle
the MISO line according to the data to be transferred. The SPI Host interface specifies that
first a SMsg pair is exchanged.
the MISO line according to the data to be transferred. The SPI Host interface specifies that
first a SMsg pair is exchanged.
8. A SHdr pair is exchanged. Note that the payload of the message is appended to the SHdr.
9. The Node detects that the transaction is complete and that it does not wish to send more
messages to the Host at this time. It drives the SRQ line low.
10. The Host detects that SRQ has gone low and that it does not have any messages to send to
the Node. It drives the MRQ line low. Since MRQ is low, CS, SCLK and MOSI are tri-stated.
11. The Node drives the SRDY line low after MRQ goes low.
7.5 Host Message SPI Example
This section provides an example Host message exchange from master (Host) to slave (Node).
In this example, the Host is sending a version request message.
In this example, the Host is sending a version request message.
This example is a zoomed-in view of the example provided previously in Figure 2. This section
covers what happens in step 3, which includes the two SPI exchanges initiated by the Host.
covers what happens in step 3, which includes the two SPI exchanges initiated by the Host.
With any SPI Host interface message, first an MMsg or SMsg pair must be exchanged. This pair
contains information on how big the message is (from the message originator) and how much
message queue space is available (on the message destination).
contains information on how big the message is (from the message originator) and how much
message queue space is available (on the message destination).
The following diagram shows such an example:
SCLK
MISO
MOSI
0
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
Figure 31 Host Message on SPI – MMsg Pair
The SPI clock edging is configurable with a polarity and phase. In order to communicate with
the Node, the SPI clock polarity must be set to “the inactive state value of SPI clock is logic level
zero” and the SPI clock phase must be set to “data is captured on the leading edge of SPI clock
and changed on the following edge of SPI clock.” This means that the data lines (both MISO
and MOSI) are read on the SCLK rising edge and are set or cleared on the SCLK falling edge,
and is commonly referred to as CPOL=0, CPHA=0.
the Node, the SPI clock polarity must be set to “the inactive state value of SPI clock is logic level
zero” and the SPI clock phase must be set to “data is captured on the leading edge of SPI clock
and changed on the following edge of SPI clock.” This means that the data lines (both MISO
and MOSI) are read on the SCLK rising edge and are set or cleared on the SCLK falling edge,
and is commonly referred to as CPOL=0, CPHA=0.
This illustration shows that the bit streams for MISO and MOSI are:
MISO: 0110100111111111
MOSI: 1010100100000100