Intel 2760QM FF8062701065300 User Manual
Product codes
FF8062701065300
Power Management
38
Datasheet, Volume 1
4.3.2
Self Refresh
The Uncore Power Manager (PCU) may request the memory controller to place the
DRAMs in self refresh state. Self refresh per channel is supported. The BIOS can put
the channel in self refresh if software remaps memory to use a subset of all channels.
Also processor channels can enter self refresh autonomously without PCU instruction
when the package is in a package C0 state.
DRAMs in self refresh state. Self refresh per channel is supported. The BIOS can put
the channel in self refresh if software remaps memory to use a subset of all channels.
Also processor channels can enter self refresh autonomously without PCU instruction
when the package is in a package C0 state.
4.3.2.1
Self Refresh Entry
Self refresh entrance can be either disabled or triggered by an idle counter. Idle counter
always clears with any access to the memory controller and remains clear as long as
the memory controller is not drained. As soon as the memory controller is drained, the
counter starts counting, and when it reaches the idle-count, the memory controller will
place the DRAMs in self refresh state.
always clears with any access to the memory controller and remains clear as long as
the memory controller is not drained. As soon as the memory controller is drained, the
counter starts counting, and when it reaches the idle-count, the memory controller will
place the DRAMs in self refresh state.
Power may be removed from the memory controller core at this point, but the V
CCD
supply (1.5 V) to the DDR I/O must be maintained.
4.3.2.2
Self Refresh Exit
Self refresh exit can be either a message from an external unit (PCU in most cases, but
also possibly from any message-channel master) or as reaction for an incoming
transaction.
also possibly from any message-channel master) or as reaction for an incoming
transaction.
The proper actions on self refresh exit are:
• CK is enabled, and four CK cycles driven
• When proper skew between Address/Command and CK are established, assert CKE
• Issue NOPs for tXSRD cycles
• Issue ZQCL to each rank
• The global scheduler will be enabled to issue commands
• When proper skew between Address/Command and CK are established, assert CKE
• Issue NOPs for tXSRD cycles
• Issue ZQCL to each rank
• The global scheduler will be enabled to issue commands
4.3.2.3
DLL and PLL Shutdown
Self refresh, according to configuration, may be a trigger for master DLL shut-down
and PLL shut-down. The master DLL shut-down is issued by the memory controller
after the DRAMs have entered self refresh.
and PLL shut-down. The master DLL shut-down is issued by the memory controller
after the DRAMs have entered self refresh.
The PLL shut-down and wake-up is issued by the PCU. The memory controller gets a
signal from PLL indicating that the memory controller can start working again.
signal from PLL indicating that the memory controller can start working again.
4.3.3
DRAM I/O Power Management
Unused signals are tristated to save power. This includes all signals associated with an
unused memory channel.
unused memory channel.
The I/O buffer for an unused signal should be tristated (output driver disabled), the
input receiver (differential sense-amp) should be disabled. The input path must be
gated to prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
input receiver (differential sense-amp) should be disabled. The input path must be
gated to prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
4.4
DMI2/PCI Express* Power Management
Active State Power Management (ASPM) support using the L1 state.
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