User Manual (FF8062701065300)Table of ContentsIntroduction9Processor Feature Details101.1.1 Supported Technologies10Processor Platform Block Diagram Example10Interfaces111.2.1 System Memory Support111.2.2 PCI Express*11PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)121.2.3 Direct Media Interface Gen 2 (DMI2)131.2.4 Platform Environment Control Interface (PECI)13Power Management Support131.3.1 Processor Package and Core States131.3.2 System States Support131.3.3 Memory Controller131.3.4 PCI Express*13Thermal Management Support14Package Summary14Terminology14Terminology14Related Documents16Reference Documents16Interfaces17System Memory Interface172.1.1 System Memory Technology Support172.1.2 System Memory Timing Support17PCI Express* Interface172.2.1 PCI Express* Architecture172.2.1.1 Transaction Layer182.2.1.2 Data Link Layer18PCI Express* Layering Diagram18Packet Flow through the Layers182.2.1.3 Physical Layer192.2.2 PCI Express* Configuration Mechanism19DMI2/PCI Express* Interface192.3.1 DMI2 Error Flow192.3.2 DMI2 Link Down20Platform Environment Control Interface (PECI)20Technologies213.1 Intel® Virtualization Technology (Intel® VT)213.1.1 Intel® VT-x Objectives213.1.2 Intel® VT-x Features223.1.3 Intel® VT-d Objectives223.1.3.1 Intel® VT-d Features Supported233.1.3.2 Intel® VT-d Processor Feature Additions233.1.4 Intel® Virtualization Technology Processor Extensions233.2 Security Technologies243.2.1 AES Instructions243.2.2 Execute Disable Bit243.3 Intel® Hyper-Threading Technology243.4 Intel® Turbo Boost Technology253.4.1 Intel® Turbo Boost Operating Frequency253.5 Enhanced Intel® SpeedStep® Technology253.6 Intel® Advanced Vector Extensions (Intel® AVX)26Power Management274.1 ACPI States Supported274.1.1 System States274.1.2 Processor Package and Core States27System States27Package C-State Support28Core C-State Support284.1.3 Integrated Memory Controller States294.1.4 DMI2/PCI Express* Link States29System Memory Power States29DMI2/PCI Express* Link States294.1.5 G, S, and C State Combinations30Processor Core/Package Power Management304.2.1 Enhanced Intel® SpeedStep® Technology30G, S, and C State Combinations304.2.2 Low-Power Idle States31Idle Power Management Breakdown of the Processor Cores31Thread and Core C-State Entry and Exit314.2.3 Requesting Low-Power Idle States324.2.4 Core C-states32P_LVLx to MWAIT Conversion324.2.4.1 Core C0 State334.2.4.2 Core C1/C1E State334.2.4.3 Core C3 State334.2.4.4 Core C6 State334.2.4.5 Core C7 State334.2.4.6 C-State Auto-Demotion334.2.5 Package C-States344.2.5.1 Package C0354.2.5.2 Package C1/C1E35Package C-State Entry and Exit35Coordination of Core Power States at the Package Level354.2.5.3 Package C2 State364.2.5.4 Package C3 State364.2.5.5 Package C6 State364.2.6 Package C-State Power Specifications37System Memory Power Management374.3.1 CKE Power-Down37Package C-State Power Specifications374.3.2 Self Refresh384.3.2.1 Self Refresh Entry384.3.2.2 Self Refresh Exit384.3.2.3 DLL and PLL Shutdown384.3.3 DRAM I/O Power Management38DMI2/PCI Express* Power Management38Signal Descriptions41System Memory Interface41Memory Channel DDR0, DDR1, DDR2, DDR341PCI Express* Based Interface Signals42Memory Channel Miscellaneous42PCI Express* Port 1 Signals42PCI Express* Port 2 Signals43PCI Express* Port 3 Signals43DMI2/PCI Express* Port 0 Signals44PECI Signal44System Reference Clock Signals44PCI Express* Miscellaneous Signals44DMI2 to Port 0 Signals44PECI Signals44System Reference Clock (BCLK{0/1}) Signals44JTAG and TAP Signals45Serial VID Interface (SVID) Signals45JTAG and TAP Signals45SVID Signals45Processor Asynchronous Sideband and Miscellaneous Signals46Processor Asynchronous Sideband Signals46Miscellaneous Signals47Processor Power and Ground Supplies48Power and Ground Signals48Processor Signaling497.1.1 System Memory Interface Signal Groups497.1.2 PCI Express* Signals497.1.3 DMI2/PCI Express* Signals497.1.4 Platform Environmental Control Interface (PECI)497.1.4.1 Input Device Hysteresis507.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)507.1.5.1 PLL Power Supply50Input Device Hysteresis507.1.6 JTAG and Test Access Port (TAP) Signals517.1.7 Processor Sideband Signals517.1.8 Power, Ground and Sense Signals517.1.8.1 Power and Ground Lands51Power and Ground Lands517.1.8.2 Decoupling Guidelines527.1.8.3 Voltage Identification (VID)52VR Power-State Transitions54SVID Address Usage54Voltage Identification Definition557.1.9 Reserved or Unused Signals56Signal Group Summary56Signal Description Buffer Types56Signal Groups57Power-On Configuration (POC) Options59Signals with On-Die Termination59Power-On Configuration Option Lands59Absolute Maximum and Minimum Ratings607.4.1 Storage Conditions Specifications60Processor Absolute Minimum and Maximum Ratings60DC Specifications617.5.1 Voltage and Current Specifications61Voltage Specification61Current (Icc_Max and Icc_TDC) Specification627.5.2 Die Voltage Validation637.5.2.1 VCC Overshoot Specifications63VCC Overshoot Example Waveform63VCC Overshoot Specifications637.5.3 Signal DC Specifications64DDR3 Signal DC Specifications64PECI DC Specifications65System Reference Clock (BCLK{0/1}) DC Specifications66SMBus DC Specifications66JTAG and TAP Signals DC Specifications67Serial VID Interface (SVID) DC Specifications67Processor Asynchronous Sideband DC Specifications687.5.3.1 PCI Express* DC Specifications697.5.3.2 DMI2/PCI Express* DC Specifications697.5.3.3 Reset and Miscellaneous Signal DC Specifications69Miscellaneous Signals DC Specifications69Processor Land Listing71Land Name72Land Number95Package Mechanical Specifications119Size: 719 KBPages: 120Language: EnglishOpen manual
