Intel P4500 CP80617004803AA Data Sheet
Product codes
CP80617004803AA
Power Management
40
Datasheet
4.1.7
Interface State Combinations
4.2
Processor Core Power Management
While executing code, Enhanced Intel SpeedStep Technology optimizes the processors
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power
C-states have longer entry and exit latencies.
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power
C-states have longer entry and exit latencies.
Table 4-11.G, S and C State Combinations
Global
(G) State
Sleep
(S) State
Processor
Core
(C) State
Processor
State
System Clocks
Description
G0
S0
C0
Full On
On
Full On
G0
S0
C1/C1E
Auto-Halt
On
Auto-Halt
G0
S0
C3
Deep Sleep
On
Deep Sleep
G0
S0
C6
Deep Power
Down
Down
On
Deep Power Down
G1
S3
Power off
Off, except RTC
Suspend to RAM
G1
S4
Power off
Off, except RTC
Suspend to Disk
G2
S5
Power off
Off, except RTC
Soft Off
G3
NA
Power off
Power off
Hard off
Table 4-12.D, S, and C State Combination
Graphics Adapter
(D) State
Sleep (S) State
Package (C) State
Description
D0
S0
C0
Full On, Displaying
D0
S0
C1/C1E
Auto-Halt, Displaying
D0
S0
C3
Deep sleep, Displaying
D0
S0
C6
Deep Power Down,
Displaying
Displaying
D3
S0
Any
Not displaying
D3
S3
N/A
Not displaying, Graphics
Core is powered off
Core is powered off
D3
S4
N/A
Not displaying, suspend to
disk
disk